From 64dee52dd57cfe4f206b50d4160547c58360d881 Mon Sep 17 00:00:00 2001
From: Nic0w <nico.broquet@gmail.com>
Date: Wed, 5 May 2021 07:55:51 +0200
Subject: [PATCH] Satisfies clippy

---
 rp2040-hal/src/pll.rs | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/rp2040-hal/src/pll.rs b/rp2040-hal/src/pll.rs
index 02e8537..849736e 100644
--- a/rp2040-hal/src/pll.rs
+++ b/rp2040-hal/src/pll.rs
@@ -54,7 +54,7 @@ impl<S: State, D: PhaseLockedLoopDevice> PhaseLockedLoop<S, D> {
     fn transition<To: State>(self, state: To) -> PhaseLockedLoop<To, D> {
         PhaseLockedLoop {
             device: self.device,
-            state: state,
+            state,
         }
     }
 
@@ -131,7 +131,8 @@ impl<D: PhaseLockedLoopDevice> PhaseLockedLoop<Disabled, D> {
     where
         R: Into<Hertz<u64>>,
     {
-        const VCO_FREQ_RANGE: RangeInclusive<Hertz<u32>> = Hertz(400_000_000)..=Hertz(1600_000_000);
+        const VCO_FREQ_RANGE: RangeInclusive<Hertz<u32>> =
+            Hertz(400_000_000)..=Hertz(1_600_000_000);
         const POSTDIV_RANGE: Range<u8> = 1..7;
         const FBDIV_RANGE: Range<u16> = 16..320;