From 6ab9cd7ed3dbb2a1a9fe7ab1cf043a4802b7483b Mon Sep 17 00:00:00 2001
From: 9names <60134748+9names@users.noreply.github.com>
Date: Fri, 3 Dec 2021 22:48:24 +1100
Subject: [PATCH] Generate sev in sio.fifo.write()

---
 rp2040-hal/src/sio.rs | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/rp2040-hal/src/sio.rs b/rp2040-hal/src/sio.rs
index 586e86b..ff808ec 100644
--- a/rp2040-hal/src/sio.rs
+++ b/rp2040-hal/src/sio.rs
@@ -109,6 +109,9 @@ impl SioFifo {
     pub fn write(&mut self, value: u32) {
         let sio = unsafe { &(*pac::SIO::ptr()) };
         sio.fifo_wr.write(|w| unsafe { w.bits(value) });
+        // Fire off an event to the other core.
+        // This is required as the other core may be `wfe` (waiting for event)
+        cortex_m::asm::sev();
     }
 
     /// Read from the inter-core FIFO.