From 0a082c0f03657312735c0bc45d884bc297869a76 Mon Sep 17 00:00:00 2001 From: Jonathan Pallant Date: Fri, 19 Nov 2021 12:16:50 +0000 Subject: [PATCH 1/4] Changes to work with upcoming PAC 0.16. --- rp2040-hal/src/gpio/reg.rs | 71 +++++++++++++++++++++++++------------- 1 file changed, 47 insertions(+), 24 deletions(-) diff --git a/rp2040-hal/src/gpio/reg.rs b/rp2040-hal/src/gpio/reg.rs index 5058a4a..c643e30 100644 --- a/rp2040-hal/src/gpio/reg.rs +++ b/rp2040-hal/src/gpio/reg.rs @@ -7,7 +7,6 @@ use super::{ use crate::atomic_register_access::{write_bitmask_clear, write_bitmask_set}; use crate::gpio::dynpin::{DynDisabled, DynFunction, DynInput, DynOutput, DynPinMode}; use crate::pac; -use core::ptr::read_volatile; //============================================================================== // ModeFields @@ -263,9 +262,11 @@ pub(super) unsafe trait RegisterInterface { let num = self.id().num as usize; unsafe { let io = &(*pac::IO_BANK0::ptr()); - let reg = (&io.intr0).as_ptr().add(num / 8); + // There are four bits for each GPIO pin (one for each enumerator + // in the `Interrupt` enum). There are therefore eight pins per + // 32-bit register, and four registers in total. let bit_in_reg = num % 8 * 4 + interrupt as usize; - *reg |= 1 << bit_in_reg; + io.intr[num >> 3].write(|w| w.bits(1 << bit_in_reg)); } } @@ -274,13 +275,17 @@ pub(super) unsafe trait RegisterInterface { fn interrupt_status(&self, interrupt: Interrupt) -> bool { let num = self.id().num as usize; unsafe { - let cpuid = *(pac::SIO::ptr() as *const u32); let io = &(*pac::IO_BANK0::ptr()); - let reg = (&io.proc0_ints0) - .as_ptr() - .add(num / 8 + cpuid as usize * 12); - let bit_in_reg = num % 8 * 4 + interrupt as usize; - (read_volatile(reg) & (1 << bit_in_reg)) != 0 + let cpuid = *(pac::SIO::ptr() as *const u32); + // There are four bits for each GPIO pin (one for each enumerator + // in the `Interrupt` enum). There are therefore eight pins per + // 32-bit register, and four registers per CPU. + let bit_in_reg = ((num % 8) * 4) + (interrupt as usize); + if cpuid == 0 { + (io.proc0_ints[num >> 3].read().bits() & (1 << bit_in_reg)) != 0 + } else { + (io.proc1_ints[num >> 3].read().bits() & (1 << bit_in_reg)) != 0 + } } } @@ -289,13 +294,17 @@ pub(super) unsafe trait RegisterInterface { fn is_interrupt_enabled(&self, interrupt: Interrupt) -> bool { let num = self.id().num as usize; unsafe { - let cpuid = *(pac::SIO::ptr() as *const u32); let io = &(*pac::IO_BANK0::ptr()); - let reg = (&io.proc0_inte0) - .as_ptr() - .add(num / 8 + cpuid as usize * 12); + let cpuid = *(pac::SIO::ptr() as *const u32); + // There are four bits for each GPIO pin (one for each enumerator + // in the `Interrupt` enum). There are therefore eight pins per + // 32-bit register, and four registers per CPU. let bit_in_reg = num % 8 * 4 + interrupt as usize; - (read_volatile(reg) & (1 << bit_in_reg)) != 0 + if cpuid == 0 { + (io.proc0_inte[num >> 3].read().bits() & (1 << bit_in_reg)) != 0 + } else { + (io.proc1_inte[num >> 3].read().bits() & (1 << bit_in_reg)) != 0 + } } } @@ -306,9 +315,14 @@ pub(super) unsafe trait RegisterInterface { unsafe { let cpuid = *(pac::SIO::ptr() as *const u32); let io = &(*pac::IO_BANK0::ptr()); - let reg = (&io.proc0_inte0) - .as_ptr() - .add(num / 8 + cpuid as usize * 12); + // There are four bits for each GPIO pin (one for each enumerator + // in the `Interrupt` enum). There are therefore eight pins per + // 32-bit register, and four registers per CPU. + let reg = if cpuid == 0 { + io.proc0_inte[num >> 3].as_ptr() + } else { + io.proc1_inte[num >> 3].as_ptr() + }; let bit_in_reg = num % 8 * 4 + interrupt as usize; if enabled { write_bitmask_set(reg, 1 << bit_in_reg); @@ -325,11 +339,15 @@ pub(super) unsafe trait RegisterInterface { unsafe { let cpuid = *(pac::SIO::ptr() as *const u32); let io = &(*pac::IO_BANK0::ptr()); - let reg = (&io.proc0_intf0) - .as_ptr() - .add(num / 8 + cpuid as usize * 12); + // There are four bits for each GPIO pin (one for each enumerator + // in the `Interrupt` enum). There are therefore eight pins per + // 32-bit register, and four registers per CPU. let bit_in_reg = num % 8 * 4 + interrupt as usize; - (read_volatile(reg) & (1 << bit_in_reg)) != 0 + if cpuid == 0 { + (io.proc0_intf[num >> 3].read().bits() & (1 << bit_in_reg)) != 0 + } else { + (io.proc1_intf[num >> 3].read().bits() & (1 << bit_in_reg)) != 0 + } } } @@ -340,9 +358,14 @@ pub(super) unsafe trait RegisterInterface { unsafe { let cpuid = *(pac::SIO::ptr() as *const u32); let io = &(*pac::IO_BANK0::ptr()); - let reg = (&io.proc0_intf0) - .as_ptr() - .add(num / 8 + cpuid as usize * 12); + // There are four bits for each GPIO pin (one for each enumerator + // in the `Interrupt` enum). There are therefore eight pins per + // 32-bit register, and four registers per CPU. + let reg = if cpuid == 0 { + io.proc0_intf[num >> 3].as_ptr() + } else { + io.proc1_intf[num >> 3].as_ptr() + }; let bit_in_reg = num % 8 * 4 + interrupt as usize; if forced { write_bitmask_set(reg, 1 << bit_in_reg); From 23bafb6980db6ee9a60d5baf696f5ed14d8b053b Mon Sep 17 00:00:00 2001 From: Jonathan Pallant Date: Fri, 19 Nov 2021 12:22:52 +0000 Subject: [PATCH 2/4] Point at PAC release branch. --- rp2040-hal/Cargo.toml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rp2040-hal/Cargo.toml b/rp2040-hal/Cargo.toml index a9dad14..8e4ff4b 100644 --- a/rp2040-hal/Cargo.toml +++ b/rp2040-hal/Cargo.toml @@ -16,7 +16,7 @@ eh1_0_alpha = { version = "=1.0.0-alpha.5", package="embedded-hal", optional=tru embedded-time = "0.12.0" itertools = { version = "0.10.1", default-features = false } nb = "1.0" -rp2040-pac = "0.1.5" +rp2040-pac = { git = "https://github.com/rp-rs/rp2040-pac.git", branch = "release_016", version = "0.1.6" } paste = "1.0" pio = { git = "https://github.com/rp-rs/pio-rs.git", branch = "main" } usb-device = "0.2.8" From 84b903b12a498057149343ff103010fe6121ece6 Mon Sep 17 00:00:00 2001 From: Jonathan Pallant Date: Fri, 19 Nov 2021 22:22:29 +0000 Subject: [PATCH 3/4] PAC 0.1.6 is now released. --- rp2040-hal/Cargo.toml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rp2040-hal/Cargo.toml b/rp2040-hal/Cargo.toml index 8e4ff4b..7550c92 100644 --- a/rp2040-hal/Cargo.toml +++ b/rp2040-hal/Cargo.toml @@ -16,7 +16,7 @@ eh1_0_alpha = { version = "=1.0.0-alpha.5", package="embedded-hal", optional=tru embedded-time = "0.12.0" itertools = { version = "0.10.1", default-features = false } nb = "1.0" -rp2040-pac = { git = "https://github.com/rp-rs/rp2040-pac.git", branch = "release_016", version = "0.1.6" } +rp2040-pac = "0.1.6" paste = "1.0" pio = { git = "https://github.com/rp-rs/pio-rs.git", branch = "main" } usb-device = "0.2.8" From 68602fa6e1291f82f8bcaf16b2e53301c340c3d3 Mon Sep 17 00:00:00 2001 From: Jonathan Pallant Date: Fri, 19 Nov 2021 22:30:43 +0000 Subject: [PATCH 4/4] 0.1.6 had breaking changes, so I yanked it and made 0.2.0. --- rp2040-hal/Cargo.toml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rp2040-hal/Cargo.toml b/rp2040-hal/Cargo.toml index 7550c92..a6b14d7 100644 --- a/rp2040-hal/Cargo.toml +++ b/rp2040-hal/Cargo.toml @@ -16,7 +16,7 @@ eh1_0_alpha = { version = "=1.0.0-alpha.5", package="embedded-hal", optional=tru embedded-time = "0.12.0" itertools = { version = "0.10.1", default-features = false } nb = "1.0" -rp2040-pac = "0.1.6" +rp2040-pac = "0.2.0" paste = "1.0" pio = { git = "https://github.com/rp-rs/pio-rs.git", branch = "main" } usb-device = "0.2.8"