diff --git a/rp2040-hal/src/gpio/reg.rs b/rp2040-hal/src/gpio/reg.rs
index c643e30..6e2350e 100644
--- a/rp2040-hal/src/gpio/reg.rs
+++ b/rp2040-hal/src/gpio/reg.rs
@@ -109,6 +109,13 @@ impl From<DynPinMode> for ModeFields {
         fields
     }
 }
+
+/// # Safety
+///
+/// Users should only implement the [`id`] function. No default function
+/// implementations should be overridden. The implementing type must also have
+/// "control" over the corresponding pin ID, i.e. it must guarantee that each
+/// pin ID is a singleton
 pub(super) unsafe trait RegisterInterface {
     /// Provide a [`DynPinId`] identifying the set of registers controlled by
     /// this type.
diff --git a/rp2040-hal/src/pwm/reg.rs b/rp2040-hal/src/pwm/reg.rs
index a288195..27c64ac 100644
--- a/rp2040-hal/src/pwm/reg.rs
+++ b/rp2040-hal/src/pwm/reg.rs
@@ -1,5 +1,12 @@
 use super::dyn_slice::{DynSliceId, DynSliceMode};
 use pac::pwm::CH;
+
+/// # Safety
+///
+/// Users should only implement the [`id`] function. No default function
+/// implementations should be overridden. The implementing type must also have
+/// "control" over the corresponding slice ID, i.e. it must guarantee that each
+/// slice ID is a singleton
 pub(super) unsafe trait RegisterInterface {
     /// Provide a [`DynSliceId`] identifying the set of registers controlled by
     /// this type.