Fix the pico lipo example.

boards/pico_lipo_16mb/Cargo.toml

@@ -14,6 +14,15 @@ cortex-m = "0.7.2"
 rp2040-hal = { path = "../../rp2040-hal", version = "0.2.0"}
 cortex-m-rt = { version = "0.7", optional = true }
 
+[dev-dependencies]
+embedded-time = "0.12.0"
+panic-halt= "0.2.0"
+embedded-hal ="0.2.5"
+cortex-m-rtic = "0.6.0-alpha.5"
+rp2040-boot2 = "0.1.2"
+nb = "1.0"
+
+
 [features]
 default = ["rt"]
 rt = ["cortex-m-rt","rp2040-hal/rt"]

boards/pico_lipo_16mb/examples/pico_lipo_16mb_blinky.rs

@@ -24,15 +24,15 @@ use embedded_time::rate::*;
 use panic_halt as _;
 
 // Pull in any important traits
-use pico::hal::prelude::*;
+use pico_lipo_16_mb::hal::prelude::*;
 
 // A shorter alias for the Peripheral Access Crate, which provides low-level
 // register access
-use pico::hal::pac;
+use pico_lipo_16_mb::hal::pac;
 
 // A shorter alias for the Hardware Abstraction Layer, which provides
 // higher-level drivers.
-use pico::hal;
+use pico_lipo_16_mb::hal;
 
 /// The linker will place this boot block at the start of our program image. We
 /// need this to help the ROM bootloader get our code up and running.
@@ -60,7 +60,7 @@ fn main() -> ! {
     //
     // Our default is 12 MHz crystal input, 125 MHz system clock
     let clocks = hal::clocks::init_clocks_and_plls(
-        pico::XOSC_CRYSTAL_FREQ,
+        pico_lipo_16_mb::XOSC_CRYSTAL_FREQ,
         pac.XOSC,
         pac.CLOCKS,
         pac.PLL_SYS,
@@ -79,7 +79,7 @@ fn main() -> ! {
     let sio = hal::sio::Sio::new(pac.SIO);
 
     // Set the pins up according to their function on this particular board
-    let pins = pico::Pins::new(
+    let pins = pico_lipo_16_mb::Pins::new(
         pac.IO_BANK0,
         pac.PADS_BANK0,
         sio.gpio_bank0,

boards/pico_lipo_16mb/src/lib.rs

@@ -1,6 +1,6 @@
 #![no_std]
 
-extern crate rp2040_hal as hal;
+pub use rp2040_hal as hal;
 
 #[cfg(feature = "rt")]
 extern crate cortex_m_rt;