From d5a07bc398046abc99ed314eb0ddce9450e3ec2d Mon Sep 17 00:00:00 2001 From: "Jonathan Pallant (42 Technology)" Date: Mon, 27 Sep 2021 17:30:06 +0100 Subject: [PATCH] Remove hard coded clock speed from blink example. --- rp2040-hal/examples/blinky.rs | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/rp2040-hal/examples/blinky.rs b/rp2040-hal/examples/blinky.rs index edbc342..a11020e 100644 --- a/rp2040-hal/examples/blinky.rs +++ b/rp2040-hal/examples/blinky.rs @@ -25,8 +25,10 @@ use hal::pac; // A GPIO trait we need use embedded_hal::digital::v2::OutputPin; +use embedded_time::fixed_point::FixedPoint; +use rp2040_hal::clocks::Clock; -// The linker will place this boot block at the start of our program image. We +/// The linker will place this boot block at the start of our program image. We // need this to help the ROM bootloader get our code up and running. #[link_section = ".boot2"] #[used] @@ -36,9 +38,6 @@ pub static BOOT2: [u8; 256] = rp2040_boot2::BOOT_LOADER; /// if your board has a different frequency const XTAL_FREQ_HZ: u32 = 12_000_000u32; -/// Run RP2040 at 125 MHz -const SYS_FREQ_HZ: u32 = hal::pll::common_configs::PLL_SYS_125MHZ.vco_freq.0; - /// Entry point to our bare-metal application. /// /// The `#[entry]` macro ensures the Cortex-M start-up code calls this function @@ -56,7 +55,7 @@ fn main() -> ! { let mut watchdog = hal::watchdog::Watchdog::new(pac.WATCHDOG); // Configure the clocks - let _clocks = hal::clocks::init_clocks_and_plls( + let clocks = hal::clocks::init_clocks_and_plls( XTAL_FREQ_HZ, pac.XOSC, pac.CLOCKS, @@ -68,7 +67,7 @@ fn main() -> ! { .ok() .unwrap(); - let mut delay = cortex_m::delay::Delay::new(core.SYST, SYS_FREQ_HZ); + let mut delay = cortex_m::delay::Delay::new(core.SYST, clocks.system_clock.freq().integer()); // The single-cycle I/O block controls our GPIO pins let sio = hal::sio::Sio::new(pac.SIO);