mirror of
https://github.com/italicsjenga/rp-hal-boards.git
synced 2024-12-23 20:51:31 +11:00
PWM implementation (#44)
* PWM functionality * Updated prelude.rs * Added example, cleaned up the PWM HAL. * Renamed a file for clarity * Changes to address C-CTOR recommendations, only 8 PWM channels, restructuring * Forgot to remove a test function, and added a quick comment. * Cleaned up code now that PWM channels are clustered in the PAC.
This commit is contained in:
Tyler Stowell
GitHub
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commit
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34
rp2040-hal/examples/pwm_blink.rs
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34
rp2040-hal/examples/pwm_blink.rs
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@ -0,0 +1,34 @@
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#![no_std]
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#![no_main]
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use cortex_m_rt::entry;
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use embedded_hal::PwmPin;
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use panic_halt as _;
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use rp2040_hal::pwm::*;
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#[link_section = ".boot2"]
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#[used]
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pub static BOOT2: [u8; 256] = rp2040_boot2::BOOT_LOADER;
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#[entry]
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fn main() -> ! {
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let mut pac = rp2040_pac::Peripherals::take().unwrap();
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let mut pwm_pin = Pwm0::new(0);
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//Instead of having it take references to all of these pac objects, eventually this should just
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//take ownership of a GPIO pin.
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pwm_pin.default_config(&mut pac.PWM, &mut pac.PADS_BANK0, &mut pac.IO_BANK0, &mut pac.RESETS);
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pwm_pin.set_ph_correct();
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pwm_pin.enable();
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loop {
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pwm_pin.set_duty(15000);
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// TODO: Replace with proper delays once we have clocks working
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cortex_m::asm::delay(5_000_000);
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pwm_pin.set_duty(30000);
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cortex_m::asm::delay(5_000_000);
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}
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}
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@ -1,3 +1,259 @@
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//! Pulse Width Modulation (PWM)
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// See [Chapter 4 Section 5](https://datasheets.raspberrypi.org/rp2040/rp2040_datasheet.pdf) for more details
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// TODO
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//!
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//! To access the PWM pins you must call the 'split' method on the PWM. This will return a
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//! `_____` struct with access to each PWM pin:
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//!
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//! ```rust
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//! use rp2040_hal::prelude::*;
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//! let mut pac = rp2040_pac::Peripherals::take().unwrap();
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//! let pin_num = 0;
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//! let mut pwm_pin = Pwm0::new(pin_num);
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//! ```
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//!
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//! Once you have the PWM pins struct, you can take individual pins and configure them:
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//!
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//! ```rust
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//! pwm_pin.default_config(&mut pac.PWM, &mut pac.PAD_BANK0, &mut pac.IO_BANK0, &mut pac.RESETS);
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//! pwm_pin.set_duty(32767);
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//! pwm_pin.enable();
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//! ```
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//!
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//! The following configuration options are also available:
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//!
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//! ```rust
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//! pwm_pin.min_config(&pac.PWM, &pac.PAD_BANK0, &pac.IO_BANK0, &mut pac.RESETS);
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//!
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//! pwm_pin.get_duty();
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//! pwm_pin.get_max_duty();
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//!
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//! pwm_pin.set_ph_correct().unwrap(); // Run in phase correct mode
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//! pwm_pin.clr_ph_correct().unwrap(); // Don't run in phase correct mode
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//!
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//! pwm_pin.set_div_int(value: u8).unwrap(); // To set integer part of clock divider
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//! pwm_pin.set_div_frac(value: u8).unwrap(); // To set fractional part of clock divider
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//!
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//! pwm_pin.set_inv().unwrap(); // Invert the output
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//! pwm_pin.clr_inv().unwrap(); // Don't invert the output
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//!
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//! pwm_pin.set_top(value: u16).unwrap(); // To set the TOP register
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//!
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//! pwm_pin.divmode_div().unwrap(); // Default divmode. Counts up at a rate dictated by div.
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//! pwm_pin.divmode_level().unwrap(); // These 3 divmodes can be used with a PWM B pin to read PWM inputs.
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//! pwm_pin.divmode_rise().unwrap();
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//! pwm_pin.divmode_fall().unwrap();
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//! ```
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//!
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//! default_config() sets ph_correct to false, the clock divider to 1, does not invert the output, sets top to 65535, and resets the counter.
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//! min_config() leaves those registers in the state they were before it was called (Careful, this can lead to unexpected behavior)
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//! It's recommended to only call min_config() after calling default_config() on a pin that shares a PWM block.
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use embedded_hal::PwmPin;
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use crate::resets::SubsystemReset;
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use super::*;
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macro_rules! pwm {
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($PWMX:ident, $pwmx:ident, [
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$($PXi:ident: ($pxi:ident, $pwms:expr, $pins:expr, $i:expr),)+]) => {
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$(
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#[doc = "Struct for any of the "]
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#[doc = $pwms]
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#[doc = " pins"]
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pub struct $PXi {
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pin: usize
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}
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impl $PXi {
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#[doc = "Constructor for a PWM pin struct"]
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pub fn new (pin: usize) -> Self {
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let mut pin_num : usize = 255;
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for i in 0..$pins.len() {
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if (pin == $pins[i]) {
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pin_num = pin;
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}
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}
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if (pin_num == 255) {
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pin_num = $pins[0];
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}
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Self {
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pin: pin_num,
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}
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}
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// TODO: This function contains all the methods that required the PWM to have an instance of PADS_BANK0, RESETS, or IO_BANK0.
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// Since the GPIO pins take ownership of these, after the GPIO refactor, this method should be moved into gpio.rs, and the PWM
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// will instead receive a single gpio pin.
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fn init_io(&self, pwm: &mut pac::$PWMX, pad : &mut pac::PADS_BANK0, io : &mut pac::IO_BANK0, resets: &mut pac::RESETS) -> () {
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//TODO: Merge these into gpio.rs split function after GPIO refactor. At the moment, this is here because these need to be reset for
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// the PWM to work. However, because they're here, they'll be reset every time a new PWM pin is created (BAD).
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pwm.reset_bring_up(resets);
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io.reset_bring_up(resets);
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pad.gpio[self.pin].write(|w| w.ie().set_bit());
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pad.gpio[self.pin].write(|w| w.od().clear_bit());
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io.gpio[self.pin].gpio_ctrl.write_with_zero(|w| w.funcsel().pwm_a_0());
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}
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fn cc(&self) -> &pac::$pwmx::ch::CC {
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unsafe {
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&(*pac::$PWMX::ptr()).ch[$i].cc
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}
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}
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fn csr(&self) -> &pac::$pwmx::ch::CSR {
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unsafe {
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&(*pac::$PWMX::ptr()).ch[$i].csr
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}
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}
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fn ctr(&self) -> &pac::$pwmx::ch::CTR {
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unsafe {
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&(*pac::$PWMX::ptr()).ch[$i].ctr
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}
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}
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fn div(&self) -> &pac::$pwmx::ch::DIV {
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unsafe {
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&(*pac::$PWMX::ptr()).ch[$i].div
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}
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}
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fn top(&self) -> &pac::$pwmx::ch::TOP {
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unsafe {
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&(*pac::$PWMX::ptr()).ch[$i].top
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}
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}
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#[doc = "Sets up a pin with the default configurations"]
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pub fn default_config(&mut self, pwm: &mut pac::$PWMX, pad: &mut pac::PADS_BANK0, io: &mut pac::IO_BANK0, resets: &mut pac::RESETS) -> () {
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self.init_io(pwm, pad, io, resets);
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self.clr_ph_correct();
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self.set_div_int(1);
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self.set_div_frac(0);
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self.divmode_div();
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self.set_top(0xffffu16);
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self.ctr().write(|w| unsafe { w.ctr().bits(0x0000u16) }); //Reset the counter
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self.set_duty(0); //Default duty cycle of 0%
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self.clr_inv(); //Don't invert the channel
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}
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#[doc = "Sets up a pin with minimum configurations"]
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pub fn min_config(&mut self, pwm: &mut pac::$PWMX, pad: &mut pac::PADS_BANK0, io: &mut pac::IO_BANK0, resets: &mut pac::RESETS) -> () {
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self.init_io(pwm, pad, io, resets);
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}
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#[doc = "Enables phase correct mode"]
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pub fn set_ph_correct(&self) {
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self.csr().write(|w| w.ph_correct().set_bit());
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}
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#[doc = "Disales phase correct mode"]
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pub fn clr_ph_correct(&self) {
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self.csr().write(|w| w.ph_correct().clear_bit());
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}
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#[doc = "Sets the integer part of the clock divider"]
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pub fn set_div_int(&self, value: u8) {
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self.div().write(|w| unsafe { w.int().bits(value) });
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}
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#[doc = "Sets the fractional part of the clock divider"]
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pub fn set_div_frac(&self, value: u8) {
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self.div().write(|w| unsafe { w.frac().bits(value) });
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}
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#[doc = "Enables output inversion"]
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pub fn set_inv(&self) {
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if (self.pin % 2 == 0) {
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self.csr().write(|w| w.a_inv().set_bit());
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} else {
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self.csr().write(|w| w.b_inv().set_bit());
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}
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}
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#[doc = "Disables output inversion"]
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pub fn clr_inv(&self) {
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if (self.pin % 2 == 0) {
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self.csr().write(|w| w.a_inv().clear_bit());
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} else {
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self.csr().write(|w| w.b_inv().clear_bit());
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}
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}
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#[doc = "Sets the top register value"]
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pub fn set_top(&self, value: u16) {
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self.top().write(|w| unsafe { w.top().bits(value) });
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}
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#[doc = "Sets the divmode to div. Use this if you aren't reading a PWM input."]
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pub fn divmode_div(&self) {
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self.csr().write(|w| w.divmode().div());
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}
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#[doc = "Sets the divmode to level."]
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pub fn divmode_level(&self) {
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self.csr().write(|w| w.divmode().level());
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}
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#[doc = "Sets the divmode to rise."]
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pub fn divmode_rise(&self) {
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self.csr().write(|w| w.divmode().rise());
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}
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#[doc = "Sets the divmode to fall."]
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pub fn divmode_fall(&self) {
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self.csr().write(|w| w.divmode().div());
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}
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}
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impl PwmPin for $PXi {
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type Duty = u16;
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fn disable(&mut self) -> () {
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self.csr().write(|w| w.en().clear_bit());
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}
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fn enable(&mut self) -> () {
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self.csr().write(|w| w.en().set_bit());
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}
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fn get_duty(&self) -> Self::Duty {
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if (self.pin % 2 == 0) {
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self.cc().read().a().bits()
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} else {
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self.cc().read().b().bits()
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}
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}
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fn get_max_duty(&self) -> Self::Duty {
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self.top().read().top().bits()
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}
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fn set_duty(&mut self, duty: Self::Duty) {
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if (self.pin % 2 == 0) {
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self.cc().write(|w| unsafe { w.a().bits(duty) });
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} else {
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self.cc().write(|w| unsafe { w.b().bits(duty) });
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}
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}
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}
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)+}}
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pwm! {
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PWM, pwm, [
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Pwm0: (pwm0, "pwm0", [0, 1, 16, 18], 0),
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Pwm1: (pwm1, "pwm1", [2, 3, 18, 19], 1),
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Pwm2: (pwm2, "pwm2", [4, 5, 20, 21], 2),
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Pwm3: (pwm3, "pwm3", [6, 7, 22], 3),
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Pwm4: (pwm4, "pwm4", [8, 9], 4),
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Pwm5: (pwm5, "pwm5", [10, 11, 26, 27], 5),
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Pwm6: (pwm6, "pwm6", [12, 13, 28], 6),
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Pwm7: (pwm7, "pwm7", [14, 15], 7),
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]
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}
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