alex/rp-hal-boards
1
0
Fork 0
mirror of https://github.com/italicsjenga/rp-hal-boards.git synced 2024-12-26 14:01:29 +11:00
Code Issues Packages Projects Releases Wiki Activity
519 commits 1 branch 0 tags 1.4 MiB
Commit graph

26 commits

Author SHA1 Message Date
Derek Hageman a15c109e8d Change hardware divider results structure order 
Putting the quotient first makes the compiler emit slightly better
code by putting the quotient in r0 which is generally what the
intrinsics want.
 2022-04-12 08:50:56 -06:00
Derek Hageman 80c84b13ba Add ROM floating point math library 
Hook up the ROM functions to floating point intrinsics.
 2022-02-12 11:56:24 -07:00
Derek Hageman ce681b4f10 Move divider intrinsics to the new intrinsics macro 2022-02-12 11:56:24 -07:00
Jonathan 'theJPster' Pallant 385c92392b
Merge pull request #278 from Sizurka/divider-intrinsics 
Implement intrinsics for the hardware divider
 2022-02-03 19:46:00 +00:00
Jonathan 'theJPster' Pallant 4a540d041a Hide spinlock 31. 2022-01-30 16:43:59 +00:00
Jonathan 'theJPster' Pallant efda22c9ea Update spinlock docs. 2022-01-30 16:43:53 +00:00
Jonathan 'theJPster' Pallant f44f5f0e09 Make clippy happy. 2022-01-30 16:12:43 +00:00
Jonathan 'theJPster' Pallant 35a10f2bc6 Clean up critical-section impl. 
Adds new `Sio::core()` function.
 2022-01-30 16:07:40 +00:00
Jonathan 'theJPster' Pallant 7e2f8d274c Use const generics for spinlocks. 
The fewer code-generating macros we have, the better!
 2022-01-30 15:56:23 +00:00
Jonathan 'theJPster' Pallant c8c366c23d Use new spinlock API provide by PAC 0.3.0 2022-01-30 12:56:51 +00:00
Derek Hageman f279945315 Add intrinsics for the hardware divider 
Implement intrinsic functions so basic operators use the hardware divider.
 2022-01-26 19:37:06 -07:00
Derek Hageman 35704d9799 Change divider delay to explicit NOPs 
Use explicit NOPs since cortex_m::asm::delay actually delays for
longer than we need to.
 2022-01-26 19:37:06 -07:00
Derek Hageman c2d3b21d91 Make hardware divisor interrupt safe 
Copy the pico-sdk logic for save and restore of the hardware divider
for making it interrupt safe.
 2022-01-26 19:37:06 -07:00
9names 6ab9cd7ed3 Generate sev in sio.fifo.write() 2021-12-04 00:42:46 +11:00
Jonathan 'theJPster' Pallant 3a3280575f
Merge pull request #204 from rp-rs/add_sio_fifo 
Add SIO FIFO
 2021-11-25 19:05:40 +00:00
Jonathan Pallant (Ferrous Systems) 69255f7b8c Fix wfe/sev semantics. 
We must sev on write, so the other core can wfe on read.
 2021-11-25 15:14:03 +00:00
Victor Koenders 111b355da2
Fixed error in spinlock's documentation 2021-11-24 11:59:43 +01:00
Victor Koenders 88fbc38f8b
Added spinlocks 2021-11-24 08:19:42 +01:00
Jonathan Pallant 038f792e21 Apply clippy's suggestions. 2021-11-19 17:38:32 +00:00
Jonathan Pallant 68014469dd Add SIO FIFO interface. 2021-11-19 17:19:04 +00:00
Hmvp d3cb29b113
Fix doc examples and add checking (#76) 
* Fix doc examples for peripheral drivers
* Add no_run to doc examples so they can be built by CI
* Enable building doc examples in CI check workflow
 2021-08-11 10:53:42 +10:00
Rudo2204 2d1086915c Fix unsigned hardware divide/modulo 2021-07-30 10:50:58 +10:00
Andrea Nall e3be4f8025 Massive GPIO refactor 
Bring in line with atsamd-hal GPIO v2

Copied as much as possible. Docs lifted mostly as-is.

Also add sample BSP for the Feather RP2040 in boards/feather_rp2040

May include a few random fixes from currently futile attempt to get doctests working.
 2021-07-03 10:32:43 +10:00
Rudo a14cbb5819
Hardware divide/modulo support (#40) 
* Initial SIO div/mod implementation
* Implement signed/unsigned methods for HwDivider
 2021-05-29 22:26:49 +10:00
Andrea Nall 35464a1c4b typo fix, rustfmt 2021-05-10 08:29:59 -05:00
Andrea Nall 2ef1343c05 add module to manage ownership of parts of SIO 2021-05-09 22:33:36 -05:00