mirror of
https://github.com/italicsjenga/rp-hal-boards.git
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98b8e3ae9c
Set interrupt enable flags in USB driver. The flags were already being cleared in the USB driver. Update USB examples to remove interrupt flag set/check as it is no longer necessary.
560 lines
19 KiB
Rust
560 lines
19 KiB
Rust
//! Universal Serial Bus (USB)
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// See [Chapter 4 Section 1](https://datasheets.raspberrypi.org/rp2040/rp2040_datasheet.pdf) for more details
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//! ## Usage
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//!
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//! Initialize the Usb Bus forcing the VBUS detection.
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//! ```no_run
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//! use rp2040_hal::{clocks::init_clocks_and_plls, pac, sio::Sio, usb::UsbBus, watchdog::Watchdog};
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//! use usb_device::class_prelude::UsbBusAllocator;
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//!
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//! const XOSC_CRYSTAL_FREQ: u32 = 12_000_000; // Typically found in BSP crates
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//!
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//! let mut pac = pac::Peripherals::take().unwrap();
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//! let sio = Sio::new(pac.SIO);
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//! let mut watchdog = Watchdog::new(pac.WATCHDOG);
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//! let mut clocks = init_clocks_and_plls(
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//! XOSC_CRYSTAL_FREQ,
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//! pac.XOSC,
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//! pac.CLOCKS,
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//! pac.PLL_SYS,
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//! pac.PLL_USB,
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//! &mut pac.RESETS,
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//! &mut watchdog
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//! ).ok().unwrap();
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//!
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//! let usb_bus = UsbBusAllocator::new(UsbBus::new(
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//! pac.USBCTRL_REGS,
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//! pac.USBCTRL_DPRAM,
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//! clocks.usb_clock,
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//! true,
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//! &mut pac.RESETS,
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//! ));
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//! // Use the usb_bus as usual.
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//! ```
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//!
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//! See [pico_usb_serial.rs](https://github.com/rp-rs/rp-hal/tree/main/boards/pico/examples/pico_usb_serial.rs) for more complete examples
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use core::cell::RefCell;
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use crate::clocks::UsbClock;
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use crate::pac::RESETS;
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use crate::pac::USBCTRL_DPRAM;
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use crate::pac::USBCTRL_REGS;
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use crate::resets::SubsystemReset;
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use cortex_m::interrupt::{self, Mutex};
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use usb_device::{
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bus::{PollResult, UsbBus as UsbBusTrait},
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endpoint::{EndpointAddress, EndpointType},
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Result as UsbResult, UsbDirection, UsbError,
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};
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fn ep_addr_to_ep_buf_ctrl_idx(ep_addr: EndpointAddress) -> usize {
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ep_addr.index() * 2 + (if ep_addr.is_in() { 0 } else { 1 })
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}
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#[derive(Debug)]
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struct Endpoint {
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ep_type: EndpointType,
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max_packet_size: u16,
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buffer_offset: u16,
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}
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impl Endpoint {
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unsafe fn get_buf_parts(&self) -> (*mut u8, usize) {
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const DPRAM_BASE: *mut u8 = USBCTRL_DPRAM::ptr() as *mut u8;
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if self.ep_type == EndpointType::Control {
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(DPRAM_BASE.offset(0x100), 64usize)
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} else {
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(
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DPRAM_BASE.offset(0x180 + (self.buffer_offset * 64) as isize),
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self.max_packet_size as usize,
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)
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}
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}
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fn get_buf(&self) -> &'static [u8] {
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unsafe {
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let (base, len) = self.get_buf_parts();
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core::slice::from_raw_parts(base as *const _, len)
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}
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}
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fn get_buf_mut(&self) -> &'static mut [u8] {
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unsafe {
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let (base, len) = self.get_buf_parts();
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core::slice::from_raw_parts_mut(base, len)
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}
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}
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}
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struct Inner {
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ctrl_reg: USBCTRL_REGS,
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ctrl_dpram: USBCTRL_DPRAM,
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in_endpoints: [Option<Endpoint>; 16],
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out_endpoints: [Option<Endpoint>; 16],
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next_offset: u16,
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read_setup: bool,
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}
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impl Inner {
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fn new(ctrl_reg: USBCTRL_REGS, ctrl_dpram: USBCTRL_DPRAM) -> Self {
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Self {
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ctrl_reg,
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ctrl_dpram,
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in_endpoints: Default::default(),
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out_endpoints: Default::default(),
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next_offset: 0,
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read_setup: false,
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}
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}
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fn ep_allocate(
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&mut self,
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ep_addr: Option<EndpointAddress>,
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ep_dir: UsbDirection,
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ep_type: EndpointType,
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max_packet_size: u16,
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) -> UsbResult<EndpointAddress> {
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let ep_addr = ep_addr
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.or_else(|| {
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let eps = if ep_dir == UsbDirection::In {
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self.in_endpoints.iter()
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} else {
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self.out_endpoints.iter()
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};
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// find free end point
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let mut iter = eps.enumerate();
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// reserve ep0 for the control endpoint
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if ep_type != EndpointType::Control {
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iter.next();
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}
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iter.find(|(_, ep)| ep.is_none())
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.map(|(index, _)| EndpointAddress::from_parts(index, ep_dir))
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})
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.ok_or(UsbError::EndpointOverflow)?;
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let is_ep0 = ep_addr.index() == 0;
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let is_ctrl_ep = ep_type == EndpointType::Control;
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if !(is_ep0 ^ !is_ctrl_ep) {
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return Err(UsbError::Unsupported);
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}
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let eps = if ep_addr.is_in() {
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&mut self.in_endpoints
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} else {
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&mut self.out_endpoints
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};
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let maybe_ep = eps
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.get_mut(ep_addr.index())
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.ok_or(UsbError::EndpointOverflow)?;
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if maybe_ep.is_some() {
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return Err(UsbError::InvalidEndpoint);
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}
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// Validate buffer size. From datasheet (4.1.2.5):
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// Data Buffers are typically 64 bytes long as this is the max normal packet size for most FS packets.
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// For Isochronous endpoints a maximum buffer size of 1023 bytes is supported.
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// For other packet types the maximum size is 64 bytes per buffer.
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if (ep_type != EndpointType::Isochronous && max_packet_size > 64) || max_packet_size > 1023
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{
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return Err(UsbError::Unsupported);
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}
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if ep_addr.index() == 0 {
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*maybe_ep = Some(Endpoint {
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ep_type,
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max_packet_size,
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buffer_offset: 0, // not used on CTRL ep
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});
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} else {
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// size in 64bytes units.
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// NOTE: the compiler is smart enough to recognize /64 as a 6bit right shift so let's
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// keep the division here for the sake of clarity
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let aligned_sized = (max_packet_size + 63) / 64;
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if (self.next_offset + aligned_sized) > (4096 / 64) {
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return Err(UsbError::EndpointMemoryOverflow);
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}
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let buffer_offset = self.next_offset;
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self.next_offset += aligned_sized;
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*maybe_ep = Some(Endpoint {
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ep_type,
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max_packet_size,
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buffer_offset,
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});
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}
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Ok(ep_addr)
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}
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fn ep_reset_all(&mut self) {
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self.ctrl_reg
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.sie_ctrl
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.modify(|_, w| w.ep0_int_1buf().set_bit());
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// expect ctrl ep to receive on DATA first
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self.ctrl_dpram.ep_buffer_control[0].write(|w| w.pid_0().set_bit());
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self.ctrl_dpram.ep_buffer_control[1].write(|w| {
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w.available_0().set_bit();
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w.pid_0().set_bit()
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});
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for (index, ep) in itertools::interleave(
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self.in_endpoints.iter().skip(1), // skip control endpoint
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self.out_endpoints.iter().skip(1), // skip control endpoint
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)
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.enumerate()
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.filter_map(|(i, ep)| ep.as_ref().map(|ep| (i, ep)))
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{
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use pac::usbctrl_dpram::ep_control::ENDPOINT_TYPE_A;
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let ep_type = match ep.ep_type {
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EndpointType::Bulk => ENDPOINT_TYPE_A::BULK,
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EndpointType::Isochronous => ENDPOINT_TYPE_A::ISOCHRONOUS,
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EndpointType::Control => ENDPOINT_TYPE_A::CONTROL,
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EndpointType::Interrupt => ENDPOINT_TYPE_A::INTERRUPT,
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};
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// configure
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// ep 0 in&out are not part of index (skipped before enumeration)
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self.ctrl_dpram.ep_control[index].modify(|_, w| unsafe {
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w.endpoint_type().variant(ep_type);
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w.interrupt_per_buff().set_bit();
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w.enable().set_bit();
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w.buffer_address().bits(0x180 + (ep.buffer_offset << 6))
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});
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// reset OUT ep and prepare IN ep to accept data
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let buf_control = &self.ctrl_dpram.ep_buffer_control[index + 2];
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if (index & 1) == 0 {
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// first write occur on DATA0 so prepare the pid bit to be flipped
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buf_control.write(|w| w.pid_0().set_bit());
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} else {
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buf_control.write(|w| unsafe {
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w.available_0().set_bit();
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w.pid_0().clear_bit();
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w.length_0().bits(ep.max_packet_size)
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});
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}
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}
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}
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fn ep_write(&mut self, ep_addr: EndpointAddress, buf: &[u8]) -> UsbResult<usize> {
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let index = ep_addr.index();
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let ep = self
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.in_endpoints
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.get_mut(index)
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.map(Option::as_mut)
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.flatten()
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.ok_or(UsbError::InvalidEndpoint)?;
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let buf_control = &self.ctrl_dpram.ep_buffer_control[index * 2];
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if buf_control.read().available_0().bit_is_set() {
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return Err(UsbError::WouldBlock);
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}
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let ep_buf = ep.get_buf_mut();
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if ep_buf.len() < buf.len() {
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return Err(UsbError::BufferOverflow);
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}
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ep_buf[..buf.len()].copy_from_slice(buf);
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buf_control.modify(|r, w| unsafe {
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w.available_0().set_bit();
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w.length_0().bits(buf.len() as u16);
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w.full_0().set_bit();
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w.pid_0().bit(!r.pid_0().bit())
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});
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Ok(buf.len())
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}
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fn ep_read(&mut self, ep_addr: EndpointAddress, buf: &mut [u8]) -> UsbResult<usize> {
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let index = ep_addr.index();
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let ep = self
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.out_endpoints
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.get_mut(index)
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.map(Option::as_mut)
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.flatten()
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.ok_or(UsbError::InvalidEndpoint)?;
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let buf_control = &self.ctrl_dpram.ep_buffer_control[index * 2 + 1];
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let buf_control_val = buf_control.read();
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let process_setup = index == 0 && self.read_setup;
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let (ep_buf, len) = if process_setup {
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// assume we want to read the setup request
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// Next packet will be on DATA1 so clear pid_0 so it gets flipped by next buf config
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self.ctrl_dpram.ep_buffer_control[0].modify(|_, w| w.pid_0().clear_bit());
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// the OUT packet will be either data or a status zlp
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// clear setup request flag
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self.ctrl_reg.sie_status.write(|w| w.setup_rec().set_bit());
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(
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unsafe { core::slice::from_raw_parts(USBCTRL_DPRAM::ptr() as *const u8, 8) },
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8,
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)
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} else {
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if buf_control_val.full_0().bit_is_clear() {
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return Err(UsbError::WouldBlock);
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}
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let len: usize = buf_control_val.length_0().bits().into();
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(ep.get_buf(), len)
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};
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if len > buf.len() {
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return Err(UsbError::BufferOverflow);
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}
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buf[..len].copy_from_slice(&ep_buf[..len]);
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if process_setup {
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self.read_setup = false;
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// clear any out standing out flag e.g. in case a zlp got discarded
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self.ctrl_reg.buff_status.write(|w| unsafe { w.bits(2) });
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let data_length = u16::from(buf[6]) | (u16::from(buf[7]) << 8);
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let is_in_request = (buf[0] & 0x80) == 0x80;
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let expect_data_or_zlp = is_in_request || data_length != 0;
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buf_control.modify(|_, w| unsafe {
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// enable if and only if a dataphase is expected.
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w.available_0().bit(expect_data_or_zlp);
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w.length_0().bits(ep.max_packet_size);
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w.full_0().clear_bit();
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w.pid_0().set_bit()
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});
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} else {
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buf_control.modify(|r, w| unsafe {
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w.available_0().set_bit();
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w.length_0().bits(ep.max_packet_size);
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w.full_0().clear_bit();
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w.pid_0().bit(!r.pid_0().bit())
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});
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// Clear OUT flag once it is read.
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self.ctrl_reg
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.buff_status
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.write(|w| unsafe { w.bits(1 << (index * 2 + 1)) });
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}
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Ok(len)
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}
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}
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/// Usb bus
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pub struct UsbBus {
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inner: Mutex<RefCell<Inner>>,
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}
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impl UsbBus {
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/// Create new usb bus struct and bring up usb as device.
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pub fn new(
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ctrl_reg: USBCTRL_REGS,
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ctrl_dpram: USBCTRL_DPRAM,
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_pll: UsbClock,
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force_vbus_detect_bit: bool,
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resets: &mut RESETS,
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) -> Self {
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ctrl_reg.reset_bring_down(resets);
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ctrl_reg.reset_bring_up(resets);
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unsafe {
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let raw_ctrl_reg =
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core::slice::from_raw_parts_mut(USBCTRL_REGS::ptr() as *mut u32, 1 + 0x98 / 4);
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raw_ctrl_reg.fill(0);
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let raw_ctrl_pdram =
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core::slice::from_raw_parts_mut(USBCTRL_DPRAM::ptr() as *mut u32, 1 + 0xfc / 4);
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raw_ctrl_pdram.fill(0);
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}
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ctrl_reg.usb_muxing.modify(|_, w| {
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w.to_phy().set_bit();
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w.softcon().set_bit()
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});
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if force_vbus_detect_bit {
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ctrl_reg.usb_pwr.modify(|_, w| {
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w.vbus_detect().set_bit();
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w.vbus_detect_override_en().set_bit()
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});
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}
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ctrl_reg.main_ctrl.modify(|_, w| {
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w.sim_timing().clear_bit();
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w.host_ndevice().clear_bit();
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w.controller_en().set_bit()
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});
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Self {
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inner: Mutex::new(RefCell::new(Inner::new(ctrl_reg, ctrl_dpram))),
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}
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}
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}
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impl UsbBusTrait for UsbBus {
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fn alloc_ep(
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&mut self,
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ep_dir: UsbDirection,
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ep_addr: Option<EndpointAddress>,
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ep_type: EndpointType,
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max_packet_size: u16,
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_interval: u8,
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) -> UsbResult<EndpointAddress> {
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interrupt::free(|cs| {
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let mut inner = self.inner.borrow(cs).borrow_mut();
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inner.ep_allocate(ep_addr, ep_dir, ep_type, max_packet_size)
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})
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}
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fn enable(&mut self) {
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interrupt::free(|cs| {
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let inner = self.inner.borrow(cs).borrow_mut();
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// at this stage ep's are expected to be in their reset state
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// TODO: is it worth having a debug_assert for that here?
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// Enable interrupt generation when a buffer is done, when the bus is reset,
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// and when a setup packet is received
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// this should be sufficient for device mode, will need more for host.
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inner.ctrl_reg.inte.modify(|_, w| {
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w.buff_status()
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.set_bit()
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.bus_reset()
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.set_bit()
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.setup_req()
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.set_bit()
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});
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// enable pull up to let the host know we exist.
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inner
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.ctrl_reg
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.sie_ctrl
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.modify(|_, w| w.pullup_en().set_bit());
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})
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}
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fn reset(&self) {
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interrupt::free(|cs| {
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let mut inner = self.inner.borrow(cs).borrow_mut();
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// clear reset flag
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inner.ctrl_reg.sie_status.write(|w| w.bus_reset().set_bit());
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inner
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.ctrl_reg
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.buff_status
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.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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// reset all endpoints
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inner.ep_reset_all();
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// Reset address register
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inner.ctrl_reg.addr_endp.reset();
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// TODO: RP2040-E5: work around implementation
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// TODO: reset all endpoints & buffer statuses
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})
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}
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fn set_device_address(&self, addr: u8) {
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interrupt::free(|cs| {
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let inner = self.inner.borrow(cs).borrow_mut();
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inner
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.ctrl_reg
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.addr_endp
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.modify(|_, w| unsafe { w.address().bits(addr & 0x3F) });
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// reset ep0
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inner.ctrl_dpram.ep_buffer_control[0].modify(|_, w| w.pid_0().set_bit());
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inner.ctrl_dpram.ep_buffer_control[1].modify(|_, w| w.pid_0().set_bit());
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})
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}
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fn write(&self, ep_addr: EndpointAddress, buf: &[u8]) -> UsbResult<usize> {
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interrupt::free(|cs| {
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let mut inner = self.inner.borrow(cs).borrow_mut();
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inner.ep_write(ep_addr, buf)
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})
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}
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fn read(&self, ep_addr: EndpointAddress, buf: &mut [u8]) -> UsbResult<usize> {
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interrupt::free(|cs| {
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let mut inner = self.inner.borrow(cs).borrow_mut();
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inner.ep_read(ep_addr, buf)
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})
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}
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fn set_stalled(&self, ep_addr: EndpointAddress, stalled: bool) {
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interrupt::free(|cs| {
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let inner = self.inner.borrow(cs).borrow_mut();
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if ep_addr.index() == 0 {
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inner.ctrl_reg.ep_stall_arm.modify(|_, w| {
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if ep_addr.is_in() {
|
|
w.ep0_in().bit(stalled)
|
|
} else {
|
|
w.ep0_out().bit(stalled)
|
|
}
|
|
});
|
|
}
|
|
|
|
let index = ep_addr_to_ep_buf_ctrl_idx(ep_addr);
|
|
inner.ctrl_dpram.ep_buffer_control[index].modify(|_, w| w.stall().bit(stalled));
|
|
})
|
|
}
|
|
fn is_stalled(&self, ep_addr: EndpointAddress) -> bool {
|
|
interrupt::free(|cs| {
|
|
let inner = self.inner.borrow(cs).borrow_mut();
|
|
let index = ep_addr_to_ep_buf_ctrl_idx(ep_addr);
|
|
inner.ctrl_dpram.ep_buffer_control[index]
|
|
.read()
|
|
.stall()
|
|
.bit_is_set()
|
|
})
|
|
}
|
|
fn suspend(&self) {
|
|
todo!()
|
|
}
|
|
fn resume(&self) {
|
|
todo!()
|
|
}
|
|
fn poll(&self) -> PollResult {
|
|
interrupt::free(|cs| {
|
|
let mut inner = self.inner.borrow(cs).borrow_mut();
|
|
// TODO: check for suspend request
|
|
// TODO: check for resume request
|
|
|
|
// check for bus reset
|
|
let sie_status = inner.ctrl_reg.sie_status.read();
|
|
if sie_status.bus_reset().bit_is_set() {
|
|
return PollResult::Reset;
|
|
}
|
|
|
|
let (mut ep_out, mut ep_in_complete, mut ep_setup): (u16, u16, u16) = (0, 0, 0);
|
|
|
|
let buff_status = inner.ctrl_reg.buff_status.read().bits();
|
|
if buff_status != 0 {
|
|
// IN Complete shall only be reported once.
|
|
inner
|
|
.ctrl_reg
|
|
.buff_status
|
|
.write(|w| unsafe { w.bits(0x5555_5555) });
|
|
|
|
for i in 0..32u32 {
|
|
let mask = 1 << i;
|
|
if (buff_status & mask) == mask {
|
|
if (i & 1) == 0 {
|
|
ep_in_complete |= 1 << (i / 2);
|
|
} else {
|
|
ep_out |= 1 << (i / 2);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
// check for setup request
|
|
// Only report setup if OUT has been cleared.
|
|
if sie_status.setup_rec().bit_is_set() {
|
|
ep_setup |= 1;
|
|
inner.read_setup = true;
|
|
}
|
|
|
|
if let (0, 0, 0) = (ep_out, ep_in_complete, ep_setup) {
|
|
return PollResult::None;
|
|
}
|
|
PollResult::Data {
|
|
ep_out,
|
|
ep_in_complete,
|
|
ep_setup,
|
|
}
|
|
})
|
|
}
|
|
|
|
const QUIRK_SET_ADDRESS_BEFORE_STATUS: bool = false;
|
|
}
|