mirror of
https://github.com/italicsjenga/splitspace60.git
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Initial commit - r1 schematic, must fix bottom row
This commit is contained in:
commit
cecb9c593e
243
splitspace-cache.lib
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243
splitspace-cache.lib
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EESchema-LIBRARY Version 2.3
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#encoding utf-8
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#
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# ATmega32U4
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#
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DEF ATmega32U4 U 0 40 Y Y 1 F N
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F0 "U" -900 1700 50 H V C CNN
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F1 "ATmega32U4" -650 -1550 50 H V C CNN
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F2 "" 1200 1100 50 H V C CNN
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F3 "" 1200 1100 50 H V C CNN
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$FPLIST
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TQFP44
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QFN
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$ENDFPLIST
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DRAW
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S -950 1650 900 -1450 0 1 0 N
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X (INT6/AIN0)PE6 1 1200 -650 300 L 50 50 1 1 I
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X UVCC 2 -1250 1550 300 R 50 50 1 1 I
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X D- 3 -1250 650 300 R 50 50 1 1 I
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X D+ 4 -1250 750 300 R 50 50 1 1 I
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X UGND 5 -1250 450 300 R 50 50 1 1 I
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X UCAP 6 -1250 550 300 R 50 50 1 1 I
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X VBUS 7 -1250 850 300 R 50 50 1 1 I
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X (SS/PCINT0)PB0 8 1200 1550 300 L 50 50 1 1 I
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X (SCLK/PCINT1)PB1 9 1200 1450 300 L 50 50 1 1 I
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X (PDI/MOSI/PCINT2)PB2 10 1200 1350 300 L 50 50 1 1 I
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X (RXD/INT2)PD2 20 1200 150 300 L 50 50 1 1 I
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X (ADC13/OC1B/OC4B/PCINT13)PB6 30 1200 950 300 L 50 50 1 1 I
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X (ADC1)PF1 40 1200 -950 300 L 50 50 1 1 I
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X (PDO/MISO/PCINT3)PB3 11 1200 1250 300 L 50 50 1 1 I
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X (TXD/INT3)PD3 21 1200 50 300 L 50 50 1 1 I
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X (OC3A/~OC4A~)PC6 31 1200 650 300 L 50 50 1 1 I
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X (ADC0)PF0 41 1200 -850 300 L 50 50 1 1 I
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X (OC0A/OC1C/~RTS~/PCINT7)PB7 12 1200 850 300 L 50 50 1 1 I
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X (XCK1/~CTS~)PD5 22 1200 -150 300 L 50 50 1 1 I
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X (ICP3/CLK0/OC4A)PC7 32 1200 550 300 L 50 50 1 1 I
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X AREF 42 -1250 1150 300 R 50 50 1 1 I
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X RESET 13 -1250 150 300 R 50 50 1 1 I
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X GND 23 -1250 -1250 300 R 50 50 1 1 I
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X (~HWB~)PE2 33 1200 -550 300 L 50 50 1 1 I
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X GND 43 -1250 -1150 300 R 50 50 1 1 I
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X VCC 14 -1250 1450 300 R 50 50 1 1 I
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X AVCC 24 -1250 1050 300 R 50 50 1 1 I
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X VCC 34 -1250 1350 300 R 50 50 1 1 I
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X AVCC 44 -1250 1250 300 R 50 50 1 1 I
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X GND 15 -1250 -1350 300 R 50 50 1 1 I
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X (ICP2/ADC8)PD4 25 1200 -50 300 L 50 50 1 1 I
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X GND 35 -1250 -1050 300 R 50 50 1 1 I
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X XTAL2 16 -1250 -550 300 R 50 50 1 1 I
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X (T1/~OC4D~/ADC9)PD6 26 1200 -250 300 L 50 50 1 1 I
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X (ADC7/TDI)PF7 36 1200 -1350 300 L 50 50 1 1 I
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X XTAL1 17 -1250 -450 300 R 50 50 1 1 I
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X (T0/OC4D/ADC10)PD7 27 1200 -350 300 L 50 50 1 1 I
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X (ADC6/TDO)PF6 37 1200 -1250 300 L 50 50 1 1 I
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X (OC0B/SCL/INT0)PD0 18 1200 350 300 L 50 50 1 1 I
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X (ADC11/PCINT4)PB4 28 1200 1150 300 L 50 50 1 1 I
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X (ADC5/TMS)PF5 38 1200 -1150 300 L 50 50 1 1 I
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X (SDA/INT1)PD1 19 1200 250 300 L 50 50 1 1 I
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X (ADC12/OC1A/~OC4B~/PCINT12)PB5 29 1200 1050 300 L 50 50 1 1 I
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X (ADC4/TCK)PF4 39 1200 -1050 300 L 50 50 1 1 I
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ENDDRAW
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ENDDEF
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#
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# C
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#
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DEF C C 0 10 N Y 1 F N
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F0 "C" 25 100 50 H V L CNN
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F1 "C" 25 -100 50 H V L CNN
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F2 "" 38 -150 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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$FPLIST
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C?
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C_????_*
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C_????
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SMD*_c
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Capacitor*
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$ENDFPLIST
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DRAW
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P 2 0 1 20 -80 -30 80 -30 N
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P 2 0 1 20 -80 30 80 30 N
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X ~ 1 0 150 110 D 40 40 1 1 P
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X ~ 2 0 -150 110 U 40 40 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Crystal
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#
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DEF Crystal Y 0 40 N N 1 F N
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F0 "Y" 0 150 50 H V C CNN
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F1 "Crystal" 0 -150 50 H V C CNN
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F2 "" 0 0 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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$FPLIST
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Crystal_*
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$ENDFPLIST
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DRAW
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S -50 100 50 -100 0 1 12 N
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P 2 0 1 12 -100 -50 -100 50 N
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P 2 0 1 12 100 -50 100 50 N
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X 1 1 -150 0 50 R 40 40 1 1 P
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X 2 2 150 0 50 L 40 40 1 1 P
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ENDDRAW
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ENDDEF
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#
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# D
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#
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DEF D D 0 40 N N 1 F N
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F0 "D" 0 100 50 H V C CNN
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F1 "D" 0 -100 50 H V C CNN
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F2 "" 0 0 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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$FPLIST
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Diode_*
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D-Pak_TO252AA
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*SingleDiode
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*_Diode_*
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*SingleDiode*
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$ENDFPLIST
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DRAW
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P 2 0 1 6 -50 50 -50 -50 N
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P 3 0 1 0 50 50 -50 0 50 -50 F
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X K 1 -150 0 100 R 50 50 1 1 P
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X A 2 150 0 100 L 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# GND
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#
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DEF GND #PWR 0 0 Y Y 1 F P
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F0 "#PWR" 0 -250 50 H I C CNN
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F1 "GND" 0 -150 50 H V C CNN
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F2 "" 0 0 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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DRAW
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P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
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X GND 1 0 0 0 D 50 50 1 1 W N
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ENDDRAW
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ENDDEF
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#
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# ISP
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#
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DEF ISP U 0 40 Y Y 1 F N
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F0 "U" 0 -50 60 H V C CNN
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F1 "ISP" 0 50 60 H V C CNN
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F2 "" 0 0 60 H V C CNN
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F3 "" 0 0 60 H V C CNN
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DRAW
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S -350 -150 350 150 0 1 0 N
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X MISO 1 -550 100 200 R 50 50 1 1 I
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X VCC 2 550 100 200 L 50 50 1 1 I
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X SCK 3 -550 0 200 R 50 50 1 1 I
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X MOSI 4 550 0 200 L 50 50 1 1 I
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X RST 5 -550 -100 200 R 50 50 1 1 I
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X GND 6 550 -100 200 L 50 50 1 1 I
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ENDDRAW
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ENDDEF
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#
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# LED
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#
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DEF LED D 0 40 Y N 1 F N
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F0 "D" 0 100 50 H V C CNN
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F1 "LED" 0 -100 50 H V C CNN
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F2 "" 0 0 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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$FPLIST
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LED-3MM
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LED-5MM
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LED-10MM
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LED-0603
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LED-0805
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LED-1206
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LEDV
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$ENDFPLIST
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DRAW
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P 2 0 1 0 -50 50 -50 -50 N
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P 3 0 1 0 -80 -25 -125 -65 -120 -40 N
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P 3 0 1 0 -65 -40 -110 -80 -105 -55 N
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P 3 0 1 0 50 50 -50 0 50 -50 F
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X K 1 -200 0 150 R 40 40 1 1 P
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X A 2 200 0 150 L 40 40 1 1 P
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ENDDRAW
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ENDDEF
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#
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# R
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#
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DEF R R 0 0 N Y 1 F N
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F0 "R" 80 0 50 V V C CNN
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F1 "R" 0 0 50 V V C CNN
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F2 "" -70 0 50 V V C CNN
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F3 "" 0 0 50 H V C CNN
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$FPLIST
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R_*
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Resistor_*
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$ENDFPLIST
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DRAW
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S -40 -100 40 100 0 1 10 N
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X ~ 1 0 150 50 D 50 50 1 1 P
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X ~ 2 0 -150 50 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# SW_PUSH
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#
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DEF SW_PUSH SW 0 40 N N 1 F N
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F0 "SW" 150 110 50 H V C CNN
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F1 "SW_PUSH" 0 -80 50 H V C CNN
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F2 "" 0 0 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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DRAW
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S -170 50 170 60 0 1 0 N
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P 4 0 1 0 -40 60 -30 90 30 90 40 60 N
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X 1 1 -300 0 200 R 50 50 0 1 P I
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X 2 2 300 0 200 L 50 50 0 1 P I
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ENDDRAW
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ENDDEF
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#
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# USB_OTG
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#
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DEF USB_OTG P 0 40 Y Y 1 F N
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F0 "P" 325 -125 50 H V C CNN
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F1 "USB_OTG" 0 200 50 H V C CNN
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F2 "" -50 -100 50 V V C CNN
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F3 "" -50 -100 50 V V C CNN
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$FPLIST
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USB*
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$ENDFPLIST
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DRAW
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S -250 -150 250 150 0 1 0 N
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S -205 -150 -195 -120 0 1 0 N
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S -105 -150 -95 -120 0 1 0 N
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S -5 -150 5 -120 0 1 0 N
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S 95 -150 105 -120 0 1 0 N
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S 195 -150 205 -120 0 1 0 N
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X VCC 1 -200 -300 150 U 50 50 1 1 w
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X D- 2 -100 -300 150 U 50 50 1 1 P
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X D+ 3 0 -300 150 U 50 50 1 1 P
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X ID 4 100 -300 150 U 50 50 1 1 W
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X GND 5 200 -300 150 U 50 50 1 1 W
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X shield 6 400 100 150 L 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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#End Library
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2703
splitspace.bak
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2703
splitspace.bak
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Load diff
1
splitspace.kicad_pcb
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1
splitspace.kicad_pcb
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(kicad_pcb (version 4) (host kicad "dummy file") )
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60
splitspace.pro
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60
splitspace.pro
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@ -0,0 +1,60 @@
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update=Sat 25 Jun 2016 02:28:17 PM AEST
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version=1
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last_client=kicad
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[pcbnew]
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version=1
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LastNetListRead=
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UseCmpFile=1
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PadDrill=0.600000000000
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PadDrillOvalY=0.600000000000
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PadSizeH=1.500000000000
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PadSizeV=1.500000000000
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PcbTextSizeV=1.500000000000
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PcbTextSizeH=1.500000000000
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PcbTextThickness=0.300000000000
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ModuleTextSizeV=1.000000000000
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ModuleTextSizeH=1.000000000000
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ModuleTextSizeThickness=0.150000000000
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SolderMaskClearance=0.000000000000
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SolderMaskMinWidth=0.000000000000
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DrawSegmentWidth=0.200000000000
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BoardOutlineThickness=0.100000000000
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ModuleOutlineThickness=0.150000000000
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[cvpcb]
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version=1
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NetIExt=net
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[eeschema]
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version=1
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LibDir=
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[eeschema/libraries]
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LibName1=power
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LibName2=device
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LibName3=transistors
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LibName4=conn
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LibName5=linear
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LibName6=regul
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LibName7=74xx
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LibName8=cmos4000
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LibName9=adc-dac
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LibName10=memory
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LibName11=xilinx
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LibName12=microcontrollers
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LibName13=dsp
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LibName14=microchip
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LibName15=analog_switches
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LibName16=motorola
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LibName17=texas
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LibName18=intel
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LibName19=audio
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LibName20=interface
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LibName21=digital-audio
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LibName22=philips
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LibName23=display
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LibName24=cypress
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LibName25=siliconi
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LibName26=opto
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LibName27=atmel
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LibName28=contrib
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LibName29=valves
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[general]
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version=1
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2862
splitspace.sch
Normal file
2862
splitspace.sch
Normal file
File diff suppressed because it is too large
Load diff
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