2024-01-11 08:57:41 +11:00
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use std::{io::Write, time::Duration};
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2024-01-10 15:22:28 +11:00
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2024-01-10 15:45:54 +11:00
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use anyhow::Context;
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2024-01-10 15:22:28 +11:00
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use metrics::{describe_gauge, gauge, Gauge};
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use serialport::SerialPort;
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2024-01-11 08:57:41 +11:00
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use termcolor::WriteColor;
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2024-01-10 15:22:28 +11:00
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pub struct Pli {
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port: Box<dyn SerialPort>,
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voltage_gauge: Gauge,
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duty_cycle: Gauge,
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2024-01-10 16:27:02 +11:00
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internal_charge_current: Gauge,
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internal_load_current: Gauge,
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2024-01-10 15:22:28 +11:00
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}
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2024-01-11 08:57:41 +11:00
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#[derive(Debug, Clone, Copy)]
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pub enum PliRequest {
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ReadRam(u8),
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}
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2024-01-10 15:22:28 +11:00
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impl Pli {
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pub fn new(serial_port: String, baud_rate: u32) -> anyhow::Result<Self> {
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let port = serialport::new(serial_port, baud_rate)
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.timeout(Duration::from_millis(250))
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.open()?;
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describe_gauge!("pl_battery_voltage", "Battery voltage");
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let voltage_gauge = gauge!("pl_battery_voltage");
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describe_gauge!("pl_duty_cycle", "Duty cycle");
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let duty_cycle = gauge!("pl_duty_cycle");
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2024-01-10 16:27:02 +11:00
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describe_gauge!("pl_internal_charge_current", "Internal charge current");
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let internal_charge_current = gauge!("pl_internal_charge_current");
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describe_gauge!("pl_internal_load_current", "Internal load current");
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let internal_load_current = gauge!("pl_internal_load_current");
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Ok(Self {
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port,
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voltage_gauge,
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duty_cycle,
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internal_charge_current,
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internal_load_current,
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2024-01-10 15:22:28 +11:00
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})
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}
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pub fn refresh(&mut self) {
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if let Ok(batv) = self.read_ram(PlRamAddress::Batv) {
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self.voltage_gauge.set((batv as f64) * (4. / 10.));
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}
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if let Ok(duty_cycle) = self.read_ram(PlRamAddress::Dutycyc) {
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self.duty_cycle.set((duty_cycle as f64) / 255.);
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}
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if let Ok(internal_charge_current) = self.read_ram(PlRamAddress::Cint) {
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self.internal_charge_current
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.set((internal_charge_current as f64) * (4. / 10.));
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}
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if let Ok(internal_load_current) = self.read_ram(PlRamAddress::Lint) {
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self.internal_load_current
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.set((internal_load_current as f64) * (4. / 10.));
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}
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}
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2024-01-11 08:57:41 +11:00
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pub fn process_request(&mut self, message: PliRequest) {
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match message {
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PliRequest::ReadRam(address) => match self.read_ram(address) {
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Ok(data) => {
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let mut stdout =
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termcolor::StandardStream::stdout(termcolor::ColorChoice::Always);
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let _ = stdout.set_color(
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termcolor::ColorSpec::new().set_fg(Some(termcolor::Color::Green)),
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);
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if writeln!(&mut stdout, "Read RAM at {address}: data {data}").is_err() {
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log::warn!(
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"Failed to set stdout colour\nRead RAM at {address}: data {data}"
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);
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};
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}
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Err(e) => log::error!("RAM read error: {e:?}"),
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},
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}
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}
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2024-01-10 15:22:28 +11:00
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fn send_command(&mut self, req: [u8; 4]) {
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self.port
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.write_all(&req)
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.expect("failed to write to serial port");
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}
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fn receive<const LENGTH: usize>(&mut self) -> [u8; LENGTH] {
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let mut buf = [0; LENGTH];
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match self.port.read_exact(&mut buf) {
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Ok(_) => {}
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Err(e) => log::error!("PLI serial read error: {e:#?}"),
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}
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buf
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}
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2024-01-11 08:57:41 +11:00
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fn read_ram<T>(&mut self, address: T) -> anyhow::Result<u8>
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where
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T: Into<u8>,
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{
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self.send_command(command(20, address.into(), 0));
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let buf: [u8; 2] = self.receive();
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if buf[0] == 200 { Some(buf[1]) } else { None }
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.context(format!("Error from PLI: {}", buf[0]))
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}
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}
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2024-01-10 16:27:02 +11:00
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enum PlRamAddress {
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Dutycyc,
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Batv,
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Cint,
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Lint,
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}
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impl From<PlRamAddress> for u8 {
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fn from(value: PlRamAddress) -> Self {
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match value {
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PlRamAddress::Dutycyc => 39,
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PlRamAddress::Batv => 50,
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PlRamAddress::Cint => 213,
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PlRamAddress::Lint => 217,
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}
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}
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}
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2024-01-10 15:22:28 +11:00
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fn command(operation: u8, address: u8, data: u8) -> [u8; 4] {
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[operation, address, data, !operation]
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}
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