v1.9.9-pre-13: optionally log pl accumulators

Cargo.lock

@@ -239,7 +239,7 @@ checksum = "613afe47fcd5fac7ccf1db93babcb082c5994d996f20b8b159f2ad1658eb5724"
 
 [[package]]
 name = "charge-controller-supervisor"
-version = "1.9.9-pre-12"
+version = "1.9.9-pre-13"
 dependencies = [
  "chrono",
  "clap",
@@ -2203,7 +2203,7 @@ dependencies = [
 
 [[package]]
 name = "tesla-charge-controller"
-version = "1.9.9-pre-12"
+version = "1.9.9-pre-13"
 dependencies = [
  "chrono",
  "clap",

Cargo.toml

@@ -4,7 +4,7 @@ default-members = ["charge-controller-supervisor"]
 resolver = "2"
 
 [workspace.package]
-version = "1.9.9-pre-12"
+version = "1.9.9-pre-13"
 
 [workspace.lints.clippy]
 pedantic = "warn"

charge-controller-supervisor/src/pl.rs

@@ -104,6 +104,9 @@ pub enum PliRequest {
     SetRegulatorState(RegulatorState),
 }
 
+static SHOULD_SHOW_ACCUMULATORS: std::sync::LazyLock<bool> =
+    std::sync::LazyLock::new(|| std::env::var("SHOULD_SHOW_ACCUMULATORS").is_ok());
+
 impl Pli {
     pub fn new(
         serial_port: &str,
@@ -183,6 +186,34 @@ impl Pli {
     }
 
     async fn read_state(&mut self) -> eyre::Result<PlState> {
+        if *SHOULD_SHOW_ACCUMULATORS {
+            let int_acc_lsb = self.read_ram(PlRamAddress::Ciacc1).await?;
+            let int_acc = self.read_ram(PlRamAddress::Ciacc2).await?;
+            let int_acc_msb = self.read_ram(PlRamAddress::Ciacc3).await?;
+            println!("internal charge ah accumulator: lsb {int_acc_lsb:#X?}, middle: {int_acc:#X?}, msb: {int_acc_msb:#X?}");
+            let mut internal_charge_ah_accumulator = u16::from(int_acc_msb) << 9;
+            internal_charge_ah_accumulator |= u16::from(int_acc) << 1;
+            internal_charge_ah_accumulator |= u16::from(int_acc_lsb & 0b1);
+            println!("\t\t-->which is: {internal_charge_ah_accumulator:#X?}");
+            let int_charge_low = self.read_ram(PlRamAddress::Ciahl).await?;
+            let int_charge_high = self.read_ram(PlRamAddress::Ciahh).await?;
+            let int_charge = u16::from_le_bytes([int_charge_low, int_charge_high]);
+            println!("internal charge ah: low {int_charge_low:#X?}, high {int_charge_high:#X?}, total: {int_charge}Ah");
+
+            let int_load_acc_lsb = self.read_ram(PlRamAddress::Liacc1).await?;
+            let int_load_acc = self.read_ram(PlRamAddress::Liacc2).await?;
+            let int_load_acc_msb = self.read_ram(PlRamAddress::Liacc3).await?;
+            println!("internal charge ah accumulator: lsb {int_load_acc_lsb:#X?}, middle: {int_load_acc:#X?}, msb: {int_load_acc_msb:#X?}");
+            let mut internal_load_ah_accumulator = u16::from(int_load_acc_msb) << 9;
+            internal_load_ah_accumulator |= u16::from(int_load_acc) << 1;
+            internal_load_ah_accumulator |= u16::from(int_load_acc_lsb & 0b1);
+            println!("\t\t-->which is: {internal_load_ah_accumulator:#X?}");
+            let int_load_low = self.read_ram(PlRamAddress::Liahl).await?;
+            let int_load_high = self.read_ram(PlRamAddress::Liahh).await?;
+            let int_load = u16::from_le_bytes([int_load_low, int_load_high]);
+            println!("internal charge ah: low {int_load_low:#X?}, high {int_load_high:#X?}, total: {int_load}Ah");
+        }
+
         Ok(PlState {
             battery_voltage: f64::from(self.read_ram(PlRamAddress::Batv).await?) * (4. / 10.),
             target_voltage: f64::from(self.read_ram(PlRamAddress::Vreg).await?) * (4. / 10.),
@@ -259,6 +290,26 @@ enum PlRamAddress {
     Vreg,
     Cint,
     Lint,
+    Ciacc1,
+    Ciacc2,
+    Ciacc3,
+    Ciahl,
+    Ciahh,
+    Ceacc1,
+    Ceacc2,
+    Ceacc3,
+    Ceahl,
+    Ceahh,
+    Liacc1,
+    Liacc2,
+    Liacc3,
+    Liahl,
+    Liahh,
+    Leacc1,
+    Leacc2,
+    Leacc3,
+    Leahl,
+    Leahh,
 }
 
 impl From<PlRamAddress> for u8 {
@@ -274,6 +325,26 @@ impl From<PlRamAddress> for u8 {
             PlRamAddress::Vreg => 105,
             PlRamAddress::Cint => 213,
             PlRamAddress::Lint => 217,
+            PlRamAddress::Ciacc1 => 0xB9,
+            PlRamAddress::Ciacc2 => 0xBA,
+            PlRamAddress::Ciacc3 => 0xBB,
+            PlRamAddress::Ciahl => 0xBC,
+            PlRamAddress::Ciahh => 0xBD,
+            PlRamAddress::Ceacc1 => 0xBE,
+            PlRamAddress::Ceacc2 => 0xBF,
+            PlRamAddress::Ceacc3 => 0xC0,
+            PlRamAddress::Ceahl => 0xC1,
+            PlRamAddress::Ceahh => 0xC2,
+            PlRamAddress::Liacc1 => 0xC3,
+            PlRamAddress::Liacc2 => 0xC4,
+            PlRamAddress::Liacc3 => 0xC5,
+            PlRamAddress::Liahl => 0xC6,
+            PlRamAddress::Liahh => 0xC7,
+            PlRamAddress::Leacc1 => 0xC8,
+            PlRamAddress::Leacc2 => 0xC9,
+            PlRamAddress::Leacc3 => 0xCA,
+            PlRamAddress::Leahl => 0xCB,
+            PlRamAddress::Leahh => 0xCC,
         }
     }
 }