diff --git a/charge-controller-supervisor/src/pl.rs b/charge-controller-supervisor/src/pl.rs
index 4788d0c..54c105b 100644
--- a/charge-controller-supervisor/src/pl.rs
+++ b/charge-controller-supervisor/src/pl.rs
@@ -22,6 +22,14 @@ pub struct PlState {
pub internal_load_current: f64,
pub battery_temp: f64,
pub regulator_state: RegulatorState,
+ // pub internal_charge_ah_accumulator: u16,
+ // pub external_charge_ah_accumulator: u16,
+ // pub internal_load_ah_accumulator: u16,
+ // pub external_load_ah_accumulator: u16,
+ // pub internal_charge_ah: u16,
+ // pub external_charge_ah: u16,
+ // pub internal_load_ah: u16,
+ // pub external_load_ah: u16,
}
#[derive(Debug, Clone, Copy, Serialize, Deserialize)]
@@ -104,9 +112,6 @@ pub enum PliRequest {
SetRegulatorState(RegulatorState),
}
-static SHOULD_SHOW_ACCUMULATORS: std::sync::LazyLock<bool> =
- std::sync::LazyLock::new(|| std::env::var("SHOULD_SHOW_ACCUMULATORS").is_ok());
-
impl Pli {
pub fn new(
serial_port: &str,
@@ -186,33 +191,45 @@ impl Pli {
}
async fn read_state(&mut self) -> eyre::Result<PlState> {
- if *SHOULD_SHOW_ACCUMULATORS {
- let int_acc_lsb = self.read_ram(PlRamAddress::Ciacc1).await?;
- let int_acc = self.read_ram(PlRamAddress::Ciacc2).await?;
- let int_acc_msb = self.read_ram(PlRamAddress::Ciacc3).await?;
- println!("internal charge ah accumulator: lsb {int_acc_lsb:#X?}, middle: {int_acc:#X?}, msb: {int_acc_msb:#X?}");
- let mut internal_charge_ah_accumulator = u16::from(int_acc_msb) << 9;
- internal_charge_ah_accumulator |= u16::from(int_acc) << 1;
- internal_charge_ah_accumulator |= u16::from(int_acc_lsb & 0b1);
- println!("\t\t-->which is: {internal_charge_ah_accumulator:#X?}");
- let int_charge_low = self.read_ram(PlRamAddress::Ciahl).await?;
- let int_charge_high = self.read_ram(PlRamAddress::Ciahh).await?;
- let int_charge = u16::from_le_bytes([int_charge_low, int_charge_high]);
- println!("internal charge ah: low {int_charge_low:#X?}, high {int_charge_high:#X?}, total: {int_charge}Ah");
+ // let int_charge_acc_low = self.read_ram(PlRamAddress::Ciacc1).await?;
+ // let int_charge_acc = self.read_ram(PlRamAddress::Ciacc2).await?;
+ // let int_charge_acc_high = self.read_ram(PlRamAddress::Ciacc3).await?;
+ // let mut internal_charge_ah_accumulator = u16::from(int_charge_acc_high) << 9;
+ // internal_charge_ah_accumulator |= u16::from(int_charge_acc) << 1;
+ // internal_charge_ah_accumulator |= u16::from(int_charge_acc_low & 0b1);
+ // let int_charge_low = self.read_ram(PlRamAddress::Ciahl).await?;
+ // let int_charge_high = self.read_ram(PlRamAddress::Ciahh).await?;
+ // let internal_charge_ah = u16::from_le_bytes([int_charge_low, int_charge_high]);
- let int_load_acc_lsb = self.read_ram(PlRamAddress::Liacc1).await?;
- let int_load_acc = self.read_ram(PlRamAddress::Liacc2).await?;
- let int_load_acc_msb = self.read_ram(PlRamAddress::Liacc3).await?;
- println!("internal charge ah accumulator: lsb {int_load_acc_lsb:#X?}, middle: {int_load_acc:#X?}, msb: {int_load_acc_msb:#X?}");
- let mut internal_load_ah_accumulator = u16::from(int_load_acc_msb) << 9;
- internal_load_ah_accumulator |= u16::from(int_load_acc) << 1;
- internal_load_ah_accumulator |= u16::from(int_load_acc_lsb & 0b1);
- println!("\t\t-->which is: {internal_load_ah_accumulator:#X?}");
- let int_load_low = self.read_ram(PlRamAddress::Liahl).await?;
- let int_load_high = self.read_ram(PlRamAddress::Liahh).await?;
- let int_load = u16::from_le_bytes([int_load_low, int_load_high]);
- println!("internal charge ah: low {int_load_low:#X?}, high {int_load_high:#X?}, total: {int_load}Ah");
- }
+ // let int_load_acc_low = self.read_ram(PlRamAddress::Liacc1).await?;
+ // let int_load_acc = self.read_ram(PlRamAddress::Liacc2).await?;
+ // let int_load_acc_high = self.read_ram(PlRamAddress::Liacc3).await?;
+ // let mut internal_load_ah_accumulator = u16::from(int_load_acc_high) << 9;
+ // internal_load_ah_accumulator |= u16::from(int_load_acc) << 1;
+ // internal_load_ah_accumulator |= u16::from(int_load_acc_low & 0b1);
+ // let int_load_low = self.read_ram(PlRamAddress::Liahl).await?;
+ // let int_load_high = self.read_ram(PlRamAddress::Liahh).await?;
+ // let internal_load_ah = u16::from_le_bytes([int_load_low, int_load_high]);
+
+ // let ext_charge_acc_low = self.read_ram(PlRamAddress::Ceacc1).await?;
+ // let ext_charge_acc = self.read_ram(PlRamAddress::Ceacc2).await?;
+ // let ext_charge_acc_high = self.read_ram(PlRamAddress::Ceacc3).await?;
+ // let mut external_charge_ah_accumulator = u16::from(ext_charge_acc_high) << 9;
+ // external_charge_ah_accumulator |= u16::from(ext_charge_acc) << 1;
+ // external_charge_ah_accumulator |= u16::from(ext_charge_acc_low & 0b1);
+ // let ext_charge_low = self.read_ram(PlRamAddress::Ceahl).await?;
+ // let ext_charge_high = self.read_ram(PlRamAddress::Ceahh).await?;
+ // let external_charge_ah = u16::from_le_bytes([ext_charge_low, ext_charge_high]);
+
+ // let ext_load_acc_low = self.read_ram(PlRamAddress::Leacc1).await?;
+ // let ext_load_acc = self.read_ram(PlRamAddress::Leacc2).await?;
+ // let ext_load_acc_high = self.read_ram(PlRamAddress::Leacc3).await?;
+ // let mut external_load_ah_accumulator = u16::from(ext_load_acc_high) << 9;
+ // external_load_ah_accumulator |= u16::from(ext_load_acc) << 1;
+ // external_load_ah_accumulator |= u16::from(ext_load_acc_low & 0b1);
+ // let ext_load_low = self.read_ram(PlRamAddress::Leahl).await?;
+ // let ext_load_high = self.read_ram(PlRamAddress::Leahh).await?;
+ // let external_load_ah = u16::from_le_bytes([ext_load_low, ext_load_high]);
Ok(PlState {
battery_voltage: f64::from(self.read_ram(PlRamAddress::Batv).await?) * (4. / 10.),
@@ -223,6 +240,14 @@ impl Pli {
internal_load_current: f64::from(self.read_ram(PlRamAddress::Lint).await?) * (2. / 10.),
battery_temp: f64::from(self.read_ram(PlRamAddress::Battemp).await?),
regulator_state: self.read_ram(PlRamAddress::Rstate).await?.into(),
+ // internal_charge_ah_accumulator,
+ // external_charge_ah_accumulator,
+ // internal_load_ah_accumulator,
+ // external_load_ah_accumulator,
+ // internal_charge_ah,
+ // external_charge_ah,
+ // internal_load_ah,
+ // external_load_ah,
})
}
@@ -279,6 +304,7 @@ impl Pli {
}
}
+#[allow(dead_code)]
enum PlRamAddress {
Dutycyc,
Sec,