mirror of
https://github.com/italicsjenga/vello.git
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e73049fe98
Split the blend stack into register and memory segments. Do blending in registers up to that size, then spill to memory if needed. This version may regress performance on Pixel 4, as it uses common memory for the blend stack, rather than keeping that memory read-only in fine rasterization, and using a separate buffer for blend stack. This needs investigation. It's possible we'll want to have single common memory as a config option, as it pools allocations and decreases the probability of failure. Also a flaw in this version: there is no checking of memory overflow. For understanding code history: this commit largely reverts #77, but there were some intervening changes to blending, and this commit also implements the split so some of the stack is in registers. Closes #156
104 lines
3.1 KiB
GLSL
104 lines
3.1 KiB
GLSL
// SPDX-License-Identifier: Apache-2.0 OR MIT OR Unlicense
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// Various constants for the sizes of groups and tiles.
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// Much of this will be made dynamic in various ways, but for now it's easiest
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// to hardcode and keep all in one place.
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// A LG_WG_FACTOR of n scales workgroup sizes by 2^n. Use 0 for a
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// maximum workgroup size of 128, or 1 for a maximum size of 256.
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#define LG_WG_FACTOR 1
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#define WG_FACTOR (1<<LG_WG_FACTOR)
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#define TILE_WIDTH_PX 16
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#define TILE_HEIGHT_PX 16
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#define PTCL_INITIAL_ALLOC 1024
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// These should probably be renamed and/or reworked. In the binning
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// kernel, they represent the number of bins. Also, the workgroup size
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// of that kernel is equal to the number of bins, but should probably
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// be more flexible (it's 512 in the K&L paper).
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#define N_TILE_X 16
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#define N_TILE_Y (8 * WG_FACTOR)
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#define N_TILE (N_TILE_X * N_TILE_Y)
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#define LG_N_TILE (7 + LG_WG_FACTOR)
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#define N_SLICE (N_TILE / 32)
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#define GRADIENT_WIDTH 512
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// We allocate this many blend stack entries in registers, and spill
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// to memory for the overflow.
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#define BLEND_STACK_SPLIT 4
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#ifdef ERR_MALLOC_FAILED
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struct Config {
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uint n_elements; // paths
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uint n_pathseg;
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uint width_in_tiles;
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uint height_in_tiles;
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Alloc tile_alloc;
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Alloc bin_alloc;
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Alloc ptcl_alloc;
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Alloc pathseg_alloc;
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Alloc anno_alloc;
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Alloc trans_alloc;
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// new element pipeline stuff follows
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// Bounding boxes of paths, stored as int (so atomics work)
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Alloc path_bbox_alloc;
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// Monoid for draw objects
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Alloc drawmonoid_alloc;
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// BeginClip(path_ix) / EndClip
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Alloc clip_alloc;
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// Intermediate bicyclic semigroup
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Alloc clip_bic_alloc;
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// Intermediate stack
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Alloc clip_stack_alloc;
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// Clip processing results (path_ix + bbox)
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Alloc clip_bbox_alloc;
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// Bounding box per draw object
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Alloc draw_bbox_alloc;
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// Info computed in draw stage, per draw object
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Alloc drawinfo_alloc;
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// Number of transforms in scene
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// This is probably not needed.
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uint n_trans;
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// This *should* count only actual paths, but in the current
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// implementation is redundant with n_elements.
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uint n_path;
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// Total number of BeginClip and EndClip draw objects.
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uint n_clip;
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// Note: one of these offsets *could* be hardcoded to zero (as was the
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// original element stream), but for now retain flexibility.
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// Offset (in bytes) of transform stream in scene buffer
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uint trans_offset;
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// Offset (in bytes) of linewidth stream in scene
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uint linewidth_offset;
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// Offset (in bytes) of path tag stream in scene
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uint pathtag_offset;
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// Offset (in bytes) of path segment stream in scene
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uint pathseg_offset;
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// Offset (in bytes) of draw object tag stream in scene; see drawtag.h
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uint drawtag_offset;
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// Offset (in bytes) of draw payload stream in scene
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uint drawdata_offset;
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};
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#endif
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// Fill modes.
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#define MODE_NONZERO 0
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#define MODE_STROKE 1
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// Size of kernel4 clip state, in words.
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#define CLIP_STATE_SIZE 1
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// fill_mode_from_flags extracts the fill mode from tag flags.
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uint fill_mode_from_flags(uint flags) {
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return flags & 0x1;
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}
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