This has better code generation

This commit is contained in:
Gwilym Inzani 2023-09-06 00:37:23 +01:00
parent 77445b304f
commit bb57298c54

View file

@ -385,25 +385,32 @@ impl VRamManager {
let target_location = tile_reference.0.as_ptr() as *mut _; let target_location = tile_reference.0.as_ptr() as *mut _;
unsafe { unsafe {
core::arch::asm!( match tile_format {
"cmp r2, #0", TileFormat::FourBpp => core::arch::asm!(
"beq 1f", ".rept 2",
"ldmia r0!, {{r2-r5}}",
"stmia r1!, {{r2-r5}}",
"ldmia r0!, {{r2-r5}}",
"stmia r1!, {{r2-r5}}",
"1:",
"ldmia r0!, {{r2-r5}}",
"stmia r1!, {{r2-r5}}",
"ldmia r0!, {{r2-r5}}", "ldmia r0!, {{r2-r5}}",
"stmia r1!, {{r2-r5}}", "stmia r1!, {{r2-r5}}",
".endr",
inout("r0") tile_data_start => _, inout("r0") tile_data_start => _,
inout("r1") target_location => _, inout("r1") target_location => _,
inout("r2") tile_format as u32 => _, out("r2") _,
out("r3") _, out("r3") _,
out("r4") _, out("r4") _,
out("r5") _, out("r5") _,
); ),
TileFormat::EightBpp => core::arch::asm!(
".rept 4",
"ldmia r0!, {{r2-r5}}",
"stmia r1!, {{r2-r5}}",
".endr",
inout("r0") tile_data_start => _,
inout("r1") target_location => _,
out("r2") _,
out("r3") _,
out("r4") _,
out("r5") _,
),
}
} }
} }