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embedded-hal 0.2.7 -> embedded-hal-nb 1.0.0
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@ -35,7 +35,7 @@ once_cell = { version = "1.20.1", default-features = false, features = [
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"critical-section",
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"critical-section",
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] }
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] }
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critical-section = { version = "1.1.2", features = ["restore-state-u16"] }
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critical-section = { version = "1.1.2", features = ["restore-state-u16"] }
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embedded-hal = "0.2.7"
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embedded-hal-nb = "1.0.0"
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nb = "1.1"
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nb = "1.1"
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[package.metadata.docs.rs]
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[package.metadata.docs.rs]
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@ -1,6 +1,6 @@
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use core::ops::{Deref, DerefMut};
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use core::ops::{Deref, DerefMut};
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use embedded_hal::serial::{Read, Write};
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use embedded_hal_nb::serial::{Read, Write};
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use crate::memory_mapped::MemoryMapped;
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use crate::memory_mapped::MemoryMapped;
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@ -13,6 +13,14 @@ pub enum LinkPortError {
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GbaErrorBit,
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GbaErrorBit,
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}
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}
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impl embedded_hal_nb::serial::Error for LinkPortError {
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fn kind(&self) -> embedded_hal_nb::serial::ErrorKind {
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match self {
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LinkPortError::GbaErrorBit => embedded_hal_nb::serial::ErrorKind::Other,
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}
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}
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}
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pub struct LinkPortUart;
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pub struct LinkPortUart;
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impl LinkPortUart {
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impl LinkPortUart {
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@ -29,9 +37,11 @@ impl LinkPortUart {
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}
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}
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}
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}
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impl Read<u8> for LinkPortUart {
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impl embedded_hal_nb::serial::ErrorType for LinkPortUart {
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type Error = LinkPortError;
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type Error = LinkPortError;
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}
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impl Read<u8> for LinkPortUart {
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fn read(&mut self) -> Result<u8, nb::Error<LinkPortError>> {
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fn read(&mut self) -> Result<u8, nb::Error<LinkPortError>> {
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match SioControlReg::from(SIOCNT.get()) {
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match SioControlReg::from(SIOCNT.get()) {
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v if *v.error => Err(nb::Error::Other(LinkPortError::GbaErrorBit)),
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v if *v.error => Err(nb::Error::Other(LinkPortError::GbaErrorBit)),
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@ -42,8 +52,6 @@ impl Read<u8> for LinkPortUart {
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}
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}
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impl Write<u8> for LinkPortUart {
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impl Write<u8> for LinkPortUart {
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type Error = LinkPortError;
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fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> {
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fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> {
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match self.flush() {
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match self.flush() {
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Ok(_) => {
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Ok(_) => {
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