mbc5 ram addr

2023-03-03 11:25:44 +11:00 · 2023-03-03 11:25:44 +11:00 · 06031ad649
parent cbc5a634e2
commit 06031ad649
1 changed files with 1 additions and 1 deletions
--- a/src/processor/memory/rom/mbcs/mbc5.rs
+++ b/src/processor/memory/rom/mbcs/mbc5.rs
@ -73,7 +73,7 @@ impl Mbc for Mbc5 {
    fn set(&mut self, address: Address, data: u8) {
        match address {
            0x0..0x2000 => {
-                if data == 0xA {
+                if (data & 0xF) == 0xA {
                    self.ram_enabled = true
                } else {
                    self.ram_enabled = false