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mbc5 ram addr

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This commit is contained in:
Alex Janka 2023-03-03 11:25:44 +11:00
parent cbc5a634e2
commit 06031ad649
1 changed files with 1 additions and 1 deletions
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src/processor/memory/rom/mbcs/mbc5.rs
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@ -73,7 +73,7 @@ impl Mbc for Mbc5 {
fn set(&mut self, address: Address, data: u8) { fn set(&mut self, address: Address, data: u8) {
match address { match address {
0x0..0x2000 => { 0x0..0x2000 => {
if data == 0xA { if (data & 0xF) == 0xA {
self.ram_enabled = true self.ram_enabled = true
} else { } else {
self.ram_enabled = false self.ram_enabled = false