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...why did i only give the cgb 7 wram banks?

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This commit is contained in:
Alex Janka 2023-04-23 19:32:21 +10:00
parent 7287d61f15
commit 5c61c642bf
1 changed files with 3 additions and 3 deletions
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6
lib/src/processor/memory.rs
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@ -40,8 +40,8 @@ enum WramBanks {
bank: Box<[u8; 4096]>, bank: Box<[u8; 4096]>,
}, },
Cgb { Cgb {
#[serde_as(as = "Box<[[_; 4096]; 7]>")] #[serde_as(as = "Box<[[_; 4096]; 8]>")]
banks: Box<[[u8; 4096]; 7]>, banks: Box<[[u8; 4096]; 8]>,
selected: usize, selected: usize,
}, },
} }
@ -52,7 +52,7 @@ impl Wram {
bank_0: [0; 4096], bank_0: [0; 4096],
banks: if cgb { banks: if cgb {
WramBanks::Cgb { WramBanks::Cgb {
banks: Box::new([[0; 4096]; 7]), banks: Box::new([[0; 4096]; 8]),
selected: 0, selected: 0,
} }
} else { } else {