cleanup
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77838fec27
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@ -35,7 +35,6 @@ impl MaybeBufferedSram {
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.read(true)
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.read(true)
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.open(path)
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.open(path)
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.unwrap();
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.unwrap();
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// writer.read_exact(&mut buf).unwrap();
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writer.read_to_end(&mut buf).unwrap();
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writer.read_to_end(&mut buf).unwrap();
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Some(writer)
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Some(writer)
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} else {
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} else {
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@ -140,12 +139,6 @@ impl Rom {
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let _gbc_flag = data[0x143];
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let _gbc_flag = data[0x143];
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// if _gbc_flag & 0b10000000 == 0 {
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// get_cgb_compat_palette(&data);
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// } else {
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// println!("CGB game");
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// }
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let _sgb_flag = data[0x146];
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let _sgb_flag = data[0x146];
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let rom_size = data[0x148];
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let rom_size = data[0x148];
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let ram_size = data[0x149];
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let ram_size = data[0x149];
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@ -52,6 +52,42 @@ impl Mbc1 {
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bank_mode: BankingMode::Simple,
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bank_mode: BankingMode::Simple,
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}
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}
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}
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}
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fn get_rom_addr(&self, address: Address) -> usize {
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(match address {
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0x0..0x4000 => match self.bank_mode {
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BankingMode::Simple => address as usize,
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BankingMode::Advanced => {
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(address as usize) + (self.upper_banks as usize * 512 * KB)
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}
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},
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0x4000..0x8000 => {
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(address - 0x4000) as usize
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+ (ROM_BANK_SIZE * self.rom_bank as usize)
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+ (self.upper_banks as usize * 512 * KB)
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}
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0xA000..0xC000 => panic!("passed ram address to rom address function"),
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_ => panic!("address {address} incompatible with MBC1"),
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} % self.rom_len)
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}
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fn get_ram_addr(&self, address: Address) -> usize {
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match address {
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0x0..0x8000 => panic!("passed rom address to ram address function"),
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0xA000..0xC000 => match self.bank_mode {
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BankingMode::Simple => {
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(address - 0xA000) as usize + (RAM_BANK_SIZE * self.ram_bank as usize)
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}
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BankingMode::Advanced => {
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(address - 0xA000) as usize
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+ (RAM_BANK_SIZE * self.ram_bank as usize)
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+ (self.upper_banks as usize * 16 * KB)
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}
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},
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_ => panic!("address {address} incompatible with MBC1"),
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}
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}
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}
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}
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impl Mbc for Mbc1 {
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impl Mbc for Mbc1 {
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@ -131,41 +167,3 @@ impl Mbc for Mbc1 {
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})
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})
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}
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}
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}
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}
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impl Mbc1 {
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fn get_rom_addr(&self, address: Address) -> usize {
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(match address {
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0x0..0x4000 => match self.bank_mode {
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BankingMode::Simple => address as usize,
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BankingMode::Advanced => {
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(address as usize) + (self.upper_banks as usize * 512 * KB)
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}
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},
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0x4000..0x8000 => {
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(address - 0x4000) as usize
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+ (ROM_BANK_SIZE * self.rom_bank as usize)
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+ (self.upper_banks as usize * 512 * KB)
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}
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0xA000..0xC000 => panic!("passed ram address to rom address function"),
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_ => panic!("address {address} incompatible with MBC1"),
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} % self.rom_len)
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}
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fn get_ram_addr(&self, address: Address) -> usize {
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match address {
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0x0..0x8000 => panic!("passed rom address to ram address function"),
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0xA000..0xC000 => match self.bank_mode {
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BankingMode::Simple => {
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(address - 0xA000) as usize + (RAM_BANK_SIZE * self.ram_bank as usize)
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}
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BankingMode::Advanced => {
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(address - 0xA000) as usize
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+ (RAM_BANK_SIZE * self.ram_bank as usize)
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+ (self.upper_banks as usize * 16 * KB)
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}
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},
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_ => panic!("address {address} incompatible with MBC1"),
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}
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}
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}
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@ -28,36 +28,6 @@ enum RamBank {
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Rtc(RtcRegister),
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Rtc(RtcRegister),
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}
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}
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trait AsRtcRegister {
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fn get_rtc_register(&self, register: &RtcRegister, is_halted: bool) -> u8;
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fn set_rtc_register(&mut self, register: &RtcRegister, data: u8);
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}
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// impl AsRtcRegister for DateTime<Local> {
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// fn get_rtc_register(&self, register: &RtcRegister, is_halted: bool) -> u8 {
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// match register {
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// RtcRegister::Seconds => self.second() as u8,
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// RtcRegister::Minutes => self.minute() as u8,
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// RtcRegister::Hours => self.hour() as u8,
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// RtcRegister::DayCounterLsb => 0,
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// RtcRegister::Misc => set_or_clear_bit(0, 6, is_halted),
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// }
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// }
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// fn set_rtc_register(&mut self, register: &RtcRegister, data: u8) {
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// let maybe = match register {
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// RtcRegister::Seconds => self.with_second(data as u32),
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// RtcRegister::Minutes => self.with_minute(data as u32),
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// RtcRegister::Hours => self.with_hour(data as u32),
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// RtcRegister::DayCounterLsb => None,
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// RtcRegister::Misc => None,
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// };
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// if let Some(is) = maybe {
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// self.clone_from(&is);
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// }
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// }
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// }
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struct Rtc {
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struct Rtc {
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base_time: Instant,
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base_time: Instant,
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latched_time: Option<Instant>,
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latched_time: Option<Instant>,
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