fix interrupts
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parent
df8acbfa32
commit
8f3cf515a9
1 changed files with 12 additions and 7 deletions
19
src/main.rs
19
src/main.rs
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@ -54,6 +54,7 @@ pub struct Memory {
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switchable_ram: [u8; 8192],
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cpu_ram: [u8; 128],
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oam: [u8; 160],
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interrupts: u8,
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ime: bool,
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io: [u8; 76],
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}
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@ -69,6 +70,7 @@ impl Memory {
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switchable_ram: [0x0; 8192],
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cpu_ram: [0x0; 128],
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oam: [0x0; 160],
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interrupts: 0x0,
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ime: false,
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io: [0x0; 76],
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}
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@ -113,7 +115,7 @@ impl Memory {
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return self.cpu_ram[(address - 0xFF80) as usize];
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}
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0xFFFF => {
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return if self.ime { 1 } else { 0 };
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return self.interrupts;
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}
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}
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}
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@ -143,6 +145,9 @@ impl Memory {
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// println!("empty space write: {:#X} to addr {:#X}", data, address);
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}
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0xFF00..0xFF4C => {
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print!("writing to addr {:#X}\r", address);
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stdout().flush().unwrap();
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if address == 0xFF02 && data == 0x81 {
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print!("{}", self.get(0xFF01) as char);
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stdout().flush().unwrap();
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@ -155,11 +160,11 @@ impl Memory {
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0xFF80..0xFFFF => {
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self.cpu_ram[(address - 0xFF80) as usize] = data;
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}
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0xFFFF => match data {
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0x0 => self.ime = false,
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0x1 => self.ime = true,
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_ => panic!("wrote weird number to ime: {:#X}", data),
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},
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0xFFFF => {
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println!("interrupts set to {:#b}", data);
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println!(" / {:#X}", data);
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self.interrupts = data;
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}
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}
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}
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}
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@ -224,7 +229,7 @@ fn main() {
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},
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None => loop {
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cycle_num += 1;
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print_cycles(&cycle_num);
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// print_cycles(&cycle_num);
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cpu.exec_next();
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},
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}
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