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fix stupid ram stuff + cpu inits itself

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This commit is contained in:
Alex Janka 2023-02-06 12:32:10 +11:00
parent edfda4fd84
commit 9591f2123f
2 changed files with 18 additions and 31 deletions
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36
src/main.rs
View file

@ -11,7 +11,7 @@ use std::{
sync::RwLock, sync::RwLock,
}; };
use crate::processor::{gpu::GPU, Registers}; use crate::processor::Registers;
#[macro_export] #[macro_export]
macro_rules! verbose_println { macro_rules! verbose_println {
@ -68,7 +68,6 @@ type ROM = Vec<u8>;
pub struct Memory { pub struct Memory {
bootrom: ROM, bootrom: ROM,
bootrom_enabled: bool, bootrom_enabled: bool,
interrupt_table: [u8; 256],
rom: ROM, rom: ROM,
vram: [u8; 8192], vram: [u8; 8192],
ram: [u8; 8192], ram: [u8; 8192],
@ -86,7 +85,6 @@ impl Memory {
Self { Self {
bootrom, bootrom,
bootrom_enabled, bootrom_enabled,
interrupt_table: [0xFF; 256],
rom, rom,
vram: [0x0; 8192], vram: [0x0; 8192],
ram: [0x0; 8192], ram: [0x0; 8192],
@ -102,14 +100,7 @@ impl Memory {
fn get(&self, address: Address) -> u8 { fn get(&self, address: Address) -> u8 {
match address { match address {
0x0..0x100 => { 0x0..0x8000 => {
if self.bootrom_enabled {
return self.bootrom[address as usize];
} else {
return self.interrupt_table[address as usize];
}
}
0x100..0x8000 => {
// rom access // rom access
// todo - switchable rom banks // todo - switchable rom banks
if self.bootrom_enabled && (address as usize) < self.bootrom.len() { if self.bootrom_enabled && (address as usize) < self.bootrom.len() {
@ -154,13 +145,7 @@ impl Memory {
// verbose_println!("write addr: {:#X}, data: {:#X}", address, data); // verbose_println!("write addr: {:#X}, data: {:#X}", address, data);
match address { match address {
0x0..0x100 => { 0x0..0x8000 => {
if !self.bootrom_enabled {
self.interrupt_table[address as usize] = data;
// panic!("setting {:#X} to {:#X}", address, data)
}
}
0x100..0x8000 => {
// change this with MBC code... // change this with MBC code...
// println!("tried to write {:#5X} at {:#X}", data, address); // println!("tried to write {:#5X} at {:#X}", data, address);
} }
@ -274,20 +259,11 @@ fn main() {
let rom: ROM = fs::read(args.rom).expect("Could not load ROM"); let rom: ROM = fs::read(args.rom).expect("Could not load ROM");
let bootrom: ROM = fs::read(args.bootrom).expect("Could not load BootROM"); let bootrom: ROM = fs::read(args.bootrom).expect("Could not load BootROM");
let reg = Registers::default();
let mut cpu = CPU { let mut cpu = CPU::new(Memory::init(bootrom, args.run_bootrom, rom), window);
memory: Memory::init(bootrom, args.run_bootrom, rom),
reg,
last_instruction: 0x0,
last_instruction_addr: 0x0,
window,
gpu: GPU::default(),
};
if args.run_bootrom { if !args.run_bootrom {
cpu.reg.pc = 0x0; cpu.reg.pc = 0x0100;
} else {
cpu_ram_init(&mut cpu); cpu_ram_init(&mut cpu);
} }

13
src/processor/mod.rs
View file

@ -38,6 +38,17 @@ const SPEEDUP: f64 = 1.;
const FF04_SPEED: f64 = 16384.; const FF04_SPEED: f64 = 16384.;
impl CPU { impl CPU {
pub fn new(memory: Memory, window: Window) -> Self {
Self {
memory,
reg: Registers::default(),
last_instruction: 0x0,
last_instruction_addr: 0x0,
window,
gpu: GPU::default(),
}
}
pub fn exec_next(&mut self) { pub fn exec_next(&mut self) {
self.last_instruction_addr = self.reg.pc; self.last_instruction_addr = self.reg.pc;
let opcode = self.next_opcode(); let opcode = self.next_opcode();
@ -186,7 +197,7 @@ impl Default for Registers {
de: 0x00D8, de: 0x00D8,
hl: 0x014D, hl: 0x014D,
sp: 0xFFFE, sp: 0xFFFE,
pc: 0x0100, pc: 0x0000,
} }
} }
} }