ime & daa (maybe) instruction
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2 changed files with 40 additions and 18 deletions
21
src/main.rs
21
src/main.rs
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@ -81,22 +81,22 @@ impl Memory {
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return self.ram[(address - 0xE000) as usize];
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}
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0xFE00..0xFEA0 => {
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panic!("sprite attrib memory");
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panic!("sprite attrib memory read");
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}
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0xFEA0..0xFF00 => {
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panic!("empty")
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panic!("empty space read")
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}
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0xFF00..0xFF4C => {
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panic!("I/O");
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panic!("I/O read");
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}
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0xFF4C..0xFF80 => {
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panic!("empty");
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panic!("empty space 2 read");
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}
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0xFF80..0xFFFF => {
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return self.cpu_ram[(address - 0xFF80) as usize];
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}
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0xFFFF => {
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panic!("interrupt enable register");
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panic!("interrupt enable register memory read???");
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}
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}
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}
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@ -120,22 +120,22 @@ impl Memory {
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self.ram[(address - 0xE000) as usize] = data;
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}
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0xFE00..0xFEA0 => {
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panic!("sprite attrib memory");
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panic!("sprite attrib memory write");
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}
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0xFEA0..0xFF00 => {
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panic!("empty")
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panic!("empty space write")
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}
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0xFF00..0xFF4C => {
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panic!("I/O");
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panic!("I/O write");
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}
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0xFF4C..0xFF80 => {
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panic!("empty");
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panic!("empty space 2 write");
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}
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0xFF80..0xFFFF => {
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self.cpu_ram[(address - 0xFF80) as usize] = data;
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}
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0xFFFF => {
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panic!("interrupt enable register");
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panic!("interrupt enable register memory write???");
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}
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}
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}
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@ -180,6 +180,7 @@ fn main() {
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let mut cpu = CPU {
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memory: Memory::init(run_rom),
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state,
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ime: false,
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};
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match args.step_by {
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Some(step_size) => loop {
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@ -16,6 +16,7 @@ enum FLAGS {
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pub struct CPU {
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pub memory: Memory,
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pub state: State,
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pub ime: bool,
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}
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impl CPU {
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@ -39,7 +40,7 @@ impl CPU {
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self.state.bc.as_u8s.left = self.state.bc.as_u8s.left.wrapping_sub(1)
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},
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0x06 => self.state.bc.as_u8s.left = self.ld_immediate_byte(),
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0x07 => panic!("RCLA instruction: 0x07"),
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0x07 => panic!("RCLA rotate instruction: 0x07"),
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0x08 => unsafe {
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let address = self.ld_immediate_word().as_u16;
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let word = self.state.sp;
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@ -57,7 +58,7 @@ impl CPU {
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self.state.bc.as_u8s.right = self.state.bc.as_u8s.right.wrapping_sub(0x1)
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},
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0x0E => self.state.bc.as_u8s.right = self.ld_immediate_byte(),
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0x0F => panic!("RRCA instruction: 0x0F"),
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0x0F => panic!("RRCA rotate instruction: 0x0F"),
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0x10 => panic!("STOP instruction"),
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0x11 => self.state.de = self.ld_immediate_word(),
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0x12 => unsafe {
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@ -73,7 +74,7 @@ impl CPU {
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self.state.de.as_u8s.left = self.state.de.as_u8s.left.wrapping_sub(0x1)
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},
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0x16 => self.state.de.as_u8s.left = self.ld_immediate_byte(),
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0x17 => panic!("RLA instruction: 0x17"),
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0x17 => panic!("RLA rotate instruction: 0x17"),
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0x18 => unsafe {
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self.state.pc.as_u16 = self
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.state
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@ -93,7 +94,7 @@ impl CPU {
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self.state.de.as_u8s.right = self.state.de.as_u8s.right.wrapping_sub(1)
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},
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0x1E => self.state.de.as_u8s.right = self.ld_immediate_byte(),
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0x1F => panic!("RRA instruction: 0x1F"),
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0x1F => panic!("RRA rotate instruction: 0x1F"),
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0x20 => {
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let jump_size = self.ld_immediate_byte();
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if self.get_flag(FLAGS::Z) == 0 {
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@ -120,7 +121,24 @@ impl CPU {
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self.state.hl.as_u8s.left = self.state.hl.as_u8s.left.wrapping_sub(1)
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},
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0x26 => self.state.hl.as_u8s.left = self.ld_immediate_byte(),
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0x27 => panic!("DAA instruction: 0x27"),
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0x27 => unsafe {
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println!("Running DAA instruction (0x27) that I'm not too sure about...");
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if self.get_flag(FLAGS::N) == 0 {
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if self.get_flag(FLAGS::C) == 1 || self.state.af.as_u8s.left > 0x99 {
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self.state.af.as_u8s.left += 0x60;
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}
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if self.get_flag(FLAGS::H) == 1 || (self.state.af.as_u8s.left & 0x0f) > 0x09 {
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self.state.af.as_u8s.left += 0x6;
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}
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} else {
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if self.get_flag(FLAGS::C) == 1 {
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self.state.af.as_u8s.left -= 0x60;
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}
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if self.get_flag(FLAGS::H) == 1 {
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self.state.af.as_u8s.left -= 0x6;
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}
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}
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},
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0x28 => {
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let jump_size = self.ld_immediate_byte();
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if self.get_flag(FLAGS::Z) == 1 {
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@ -809,7 +827,10 @@ impl CPU {
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self.state.pc = self.pop_word()
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}
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}
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0xD9 => panic!("RETI: 0xD9"),
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0xD9 => {
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self.state.pc = self.pop_word();
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self.ime = true;
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}
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0xDA => {
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let maybe_next = self.ld_immediate_word();
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if self.get_flag(FLAGS::C) == 1 {
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@ -918,7 +939,7 @@ impl CPU {
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self.state.af.as_u8s.left = self.memory.get(address.as_u16);
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};
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}
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0xF3 => panic!("DI IME instruction: 0xF3"),
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0xF3 => self.ime = false,
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0xF4 => undefined(0xF4),
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0xF5 => self.push(self.state.af),
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0xF6 => unsafe {
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@ -938,7 +959,7 @@ impl CPU {
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let address = self.ld_immediate_word().as_u16;
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self.state.af.as_u8s.left = self.memory.get(address);
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},
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0xFB => panic!("EI IME instruction: 0xFB"),
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0xFB => self.ime = true,
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0xFC => undefined(0xFC),
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0xFD => undefined(0xFD),
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0xFE => unsafe {
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