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ime & daa (maybe) instruction

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This commit is contained in:
Alex Janka 2023-01-17 09:30:42 +11:00
parent e6cbedc59b
commit d2e1b2d3eb
2 changed files with 40 additions and 18 deletions
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21
src/main.rs
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@ -81,22 +81,22 @@ impl Memory {
return self.ram[(address - 0xE000) as usize]; return self.ram[(address - 0xE000) as usize];
} }
0xFE00..0xFEA0 => { 0xFE00..0xFEA0 => {
panic!("sprite attrib memory"); panic!("sprite attrib memory read");
} }
0xFEA0..0xFF00 => { 0xFEA0..0xFF00 => {
panic!("empty") panic!("empty space read")
} }
0xFF00..0xFF4C => { 0xFF00..0xFF4C => {
panic!("I/O"); panic!("I/O read");
} }
0xFF4C..0xFF80 => { 0xFF4C..0xFF80 => {
panic!("empty"); panic!("empty space 2 read");
} }
0xFF80..0xFFFF => { 0xFF80..0xFFFF => {
return self.cpu_ram[(address - 0xFF80) as usize]; return self.cpu_ram[(address - 0xFF80) as usize];
} }
0xFFFF => { 0xFFFF => {
panic!("interrupt enable register"); panic!("interrupt enable register memory read???");
} }
} }
} }
@ -120,22 +120,22 @@ impl Memory {
self.ram[(address - 0xE000) as usize] = data; self.ram[(address - 0xE000) as usize] = data;
} }
0xFE00..0xFEA0 => { 0xFE00..0xFEA0 => {
panic!("sprite attrib memory"); panic!("sprite attrib memory write");
} }
0xFEA0..0xFF00 => { 0xFEA0..0xFF00 => {
panic!("empty") panic!("empty space write")
} }
0xFF00..0xFF4C => { 0xFF00..0xFF4C => {
panic!("I/O"); panic!("I/O write");
} }
0xFF4C..0xFF80 => { 0xFF4C..0xFF80 => {
panic!("empty"); panic!("empty space 2 write");
} }
0xFF80..0xFFFF => { 0xFF80..0xFFFF => {
self.cpu_ram[(address - 0xFF80) as usize] = data; self.cpu_ram[(address - 0xFF80) as usize] = data;
} }
0xFFFF => { 0xFFFF => {
panic!("interrupt enable register"); panic!("interrupt enable register memory write???");
} }
} }
} }
@ -180,6 +180,7 @@ fn main() {
let mut cpu = CPU { let mut cpu = CPU {
memory: Memory::init(run_rom), memory: Memory::init(run_rom),
state, state,
ime: false,
}; };
match args.step_by { match args.step_by {
Some(step_size) => loop { Some(step_size) => loop {

37
src/processor.rs
View file

@ -16,6 +16,7 @@ enum FLAGS {
pub struct CPU { pub struct CPU {
pub memory: Memory, pub memory: Memory,
pub state: State, pub state: State,
pub ime: bool,
} }
impl CPU { impl CPU {
@ -39,7 +40,7 @@ impl CPU {
self.state.bc.as_u8s.left = self.state.bc.as_u8s.left.wrapping_sub(1) self.state.bc.as_u8s.left = self.state.bc.as_u8s.left.wrapping_sub(1)
}, },
0x06 => self.state.bc.as_u8s.left = self.ld_immediate_byte(), 0x06 => self.state.bc.as_u8s.left = self.ld_immediate_byte(),
0x07 => panic!("RCLA instruction: 0x07"), 0x07 => panic!("RCLA rotate instruction: 0x07"),
0x08 => unsafe { 0x08 => unsafe {
let address = self.ld_immediate_word().as_u16; let address = self.ld_immediate_word().as_u16;
let word = self.state.sp; let word = self.state.sp;
@ -57,7 +58,7 @@ impl CPU {
self.state.bc.as_u8s.right = self.state.bc.as_u8s.right.wrapping_sub(0x1) self.state.bc.as_u8s.right = self.state.bc.as_u8s.right.wrapping_sub(0x1)
}, },
0x0E => self.state.bc.as_u8s.right = self.ld_immediate_byte(), 0x0E => self.state.bc.as_u8s.right = self.ld_immediate_byte(),
0x0F => panic!("RRCA instruction: 0x0F"), 0x0F => panic!("RRCA rotate instruction: 0x0F"),
0x10 => panic!("STOP instruction"), 0x10 => panic!("STOP instruction"),
0x11 => self.state.de = self.ld_immediate_word(), 0x11 => self.state.de = self.ld_immediate_word(),
0x12 => unsafe { 0x12 => unsafe {
@ -73,7 +74,7 @@ impl CPU {
self.state.de.as_u8s.left = self.state.de.as_u8s.left.wrapping_sub(0x1) self.state.de.as_u8s.left = self.state.de.as_u8s.left.wrapping_sub(0x1)
}, },
0x16 => self.state.de.as_u8s.left = self.ld_immediate_byte(), 0x16 => self.state.de.as_u8s.left = self.ld_immediate_byte(),
0x17 => panic!("RLA instruction: 0x17"), 0x17 => panic!("RLA rotate instruction: 0x17"),
0x18 => unsafe { 0x18 => unsafe {
self.state.pc.as_u16 = self self.state.pc.as_u16 = self
.state .state
@ -93,7 +94,7 @@ impl CPU {
self.state.de.as_u8s.right = self.state.de.as_u8s.right.wrapping_sub(1) self.state.de.as_u8s.right = self.state.de.as_u8s.right.wrapping_sub(1)
}, },
0x1E => self.state.de.as_u8s.right = self.ld_immediate_byte(), 0x1E => self.state.de.as_u8s.right = self.ld_immediate_byte(),
0x1F => panic!("RRA instruction: 0x1F"), 0x1F => panic!("RRA rotate instruction: 0x1F"),
0x20 => { 0x20 => {
let jump_size = self.ld_immediate_byte(); let jump_size = self.ld_immediate_byte();
if self.get_flag(FLAGS::Z) == 0 { if self.get_flag(FLAGS::Z) == 0 {
@ -120,7 +121,24 @@ impl CPU {
self.state.hl.as_u8s.left = self.state.hl.as_u8s.left.wrapping_sub(1) self.state.hl.as_u8s.left = self.state.hl.as_u8s.left.wrapping_sub(1)
}, },
0x26 => self.state.hl.as_u8s.left = self.ld_immediate_byte(), 0x26 => self.state.hl.as_u8s.left = self.ld_immediate_byte(),
0x27 => panic!("DAA instruction: 0x27"), 0x27 => unsafe {
println!("Running DAA instruction (0x27) that I'm not too sure about...");
if self.get_flag(FLAGS::N) == 0 {
if self.get_flag(FLAGS::C) == 1 || self.state.af.as_u8s.left > 0x99 {
self.state.af.as_u8s.left += 0x60;
}
if self.get_flag(FLAGS::H) == 1 || (self.state.af.as_u8s.left & 0x0f) > 0x09 {
self.state.af.as_u8s.left += 0x6;
}
} else {
if self.get_flag(FLAGS::C) == 1 {
self.state.af.as_u8s.left -= 0x60;
}
if self.get_flag(FLAGS::H) == 1 {
self.state.af.as_u8s.left -= 0x6;
}
}
},
0x28 => { 0x28 => {
let jump_size = self.ld_immediate_byte(); let jump_size = self.ld_immediate_byte();
if self.get_flag(FLAGS::Z) == 1 { if self.get_flag(FLAGS::Z) == 1 {
@ -809,7 +827,10 @@ impl CPU {
self.state.pc = self.pop_word() self.state.pc = self.pop_word()
} }
} }
0xD9 => panic!("RETI: 0xD9"), 0xD9 => {
self.state.pc = self.pop_word();
self.ime = true;
}
0xDA => { 0xDA => {
let maybe_next = self.ld_immediate_word(); let maybe_next = self.ld_immediate_word();
if self.get_flag(FLAGS::C) == 1 { if self.get_flag(FLAGS::C) == 1 {
@ -918,7 +939,7 @@ impl CPU {
self.state.af.as_u8s.left = self.memory.get(address.as_u16); self.state.af.as_u8s.left = self.memory.get(address.as_u16);
}; };
} }
0xF3 => panic!("DI IME instruction: 0xF3"), 0xF3 => self.ime = false,
0xF4 => undefined(0xF4), 0xF4 => undefined(0xF4),
0xF5 => self.push(self.state.af), 0xF5 => self.push(self.state.af),
0xF6 => unsafe { 0xF6 => unsafe {
@ -938,7 +959,7 @@ impl CPU {
let address = self.ld_immediate_word().as_u16; let address = self.ld_immediate_word().as_u16;
self.state.af.as_u8s.left = self.memory.get(address); self.state.af.as_u8s.left = self.memory.get(address);
}, },
0xFB => panic!("EI IME instruction: 0xFB"), 0xFB => self.ime = true,
0xFC => undefined(0xFC), 0xFC => undefined(0xFC),
0xFD => undefined(0xFD), 0xFD => undefined(0xFD),
0xFE => unsafe { 0xFE => unsafe {