service interrupts when halted
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@ -114,7 +114,7 @@ impl CPU {
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}
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}
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fn handle_interrupts(&mut self) -> u8 {
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fn handle_interrupts(&mut self) -> u8 {
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if self.memory.ime {
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if self.memory.ime || self.halted {
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let req_and_enabled = self.memory.get(0xFF0F) & self.memory.get(0xFFFF);
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let req_and_enabled = self.memory.get(0xFF0F) & self.memory.get(0xFFFF);
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// all interrupts should last 5 cycles?
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// all interrupts should last 5 cycles?
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if get_bit(req_and_enabled, 0) {
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if get_bit(req_and_enabled, 0) {
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