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should work now (Nightly e4ca1662f 2021-05-22) (#149)

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Lokathor 2021-05-23 19:07:26 -06:00 committed by GitHub
parent 144dada16b
commit 7df5f4737f
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2 changed files with 14 additions and 6 deletions
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4
src/save/asm_routines.s
View file

@ -32,7 +32,7 @@ WramReadByteInner:
.thumb_func .thumb_func
.align 2 .align 2
WramVerifyBuf: WramVerifyBuf:
push {r4-r5, lr} push {{r4-r5, lr}}
movs r5, r0 @ set up r5 to be r0, so we can use it immediately for the return result movs r5, r0 @ set up r5 to be r0, so we can use it immediately for the return result
movs r0, #0 @ set up r0 so the default return result is false movs r0, #0 @ set up r0 so the default return result is false
ldr r4, =WramVerifyBufInner ldr r4, =WramVerifyBufInner
@ -55,7 +55,7 @@ WramVerifyBufInner:
@ Returns from the function successfully @ Returns from the function successfully
movs r0, #1 movs r0, #1
0: @ Jumps to here return the function unsuccessfully, because r0 contains 0 at this point 0: @ Jumps to here return the function unsuccessfully, because r0 contains 0 at this point
pop {r4-r5, pc} pop {{r4-r5, pc}}
.section .text .section .text

16
src/sync/statics.rs
View file

@ -100,33 +100,41 @@ unsafe fn transfer_align4_arm<T: Copy>(mut dst: *mut T, mut src: *const T) {
) )
} else if size <= 24 { } else if size <= 24 {
asm!( asm!(
"push {{r9}}",
"ldmia {0}!, {{r2-r5,r8-r9}}", "ldmia {0}!, {{r2-r5,r8-r9}}",
"stmia {1}!, {{r2-r5,r8-r9}}", "stmia {1}!, {{r2-r5,r8-r9}}",
"pop {{r9}}",
inout(reg) src, inout(reg) dst, inout(reg) src, inout(reg) dst,
out("r2") _, out("r3") _, out("r4") _, out("r5") _, out("r8") _, out("r9") _, out("r2") _, out("r3") _, out("r4") _, out("r5") _, out("r8") _,
) )
} else if size <= 28 { } else if size <= 28 {
asm!( asm!(
"push {{r9}}",
"ldmia {0}!, {{r2-r5,r8-r10}}", "ldmia {0}!, {{r2-r5,r8-r10}}",
"stmia {1}!, {{r2-r5,r8-r10}}", "stmia {1}!, {{r2-r5,r8-r10}}",
"pop {{r9}}",
inout(reg) src, inout(reg) dst, inout(reg) src, inout(reg) dst,
out("r2") _, out("r3") _, out("r4") _, out("r5") _, out("r8") _, out("r9") _, out("r2") _, out("r3") _, out("r4") _, out("r5") _, out("r8") _,
out("r10") _, out("r10") _,
) )
} else if size <= 32 { } else if size <= 32 {
asm!( asm!(
"push {{r9}}",
"ldmia {0}!, {{r2-r5,r8-r10,r12}}", "ldmia {0}!, {{r2-r5,r8-r10,r12}}",
"stmia {1}!, {{r2-r5,r8-r10,r12}}", "stmia {1}!, {{r2-r5,r8-r10,r12}}",
"pop {{r9}}",
inout(reg) src, inout(reg) dst, inout(reg) src, inout(reg) dst,
out("r2") _, out("r3") _, out("r4") _, out("r5") _, out("r8") _, out("r9") _, out("r2") _, out("r3") _, out("r4") _, out("r5") _, out("r8") _,
out("r10") _, out("r12") _, out("r10") _, out("r12") _,
) )
} else if size <= 36 { } else if size <= 36 {
asm!( asm!(
"push {{r9}}",
"ldmia {0}!, {{r2-r5,r8-r10,r12,r14}}", "ldmia {0}!, {{r2-r5,r8-r10,r12,r14}}",
"stmia {1}!, {{r2-r5,r8-r10,r12,r14}}", "stmia {1}!, {{r2-r5,r8-r10,r12,r14}}",
"pop {{r9}}",
inout(reg) src, inout(reg) dst, inout(reg) src, inout(reg) dst,
out("r2") _, out("r3") _, out("r4") _, out("r5") _, out("r8") _, out("r9") _, out("r2") _, out("r3") _, out("r4") _, out("r5") _, out("r8") _,
out("r10") _, out("r12") _, out("r14") _, out("r10") _, out("r12") _, out("r14") _,
) )
} else { } else {