2021-12-08 19:34:39 +11:00
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//! # Multicore FIFO + GPIO 'Blinky' Example
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//!
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//! This application demonstrates FIFO communication between the CPU cores on the RP2040.
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//! Core 0 will calculate and send a delay value to Core 1, which will then wait that long
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//! before toggling the LED.
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//! Core 0 will wait for Core 1 to complete this task and send an acknowledgement value.
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//!
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//! It may need to be adapted to your particular board layout and/or pin assignment.
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//!
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2022-04-18 20:49:41 +10:00
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//! See the `Cargo.toml` file for Copyright and license details.
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2021-12-08 19:34:39 +11:00
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#![no_std]
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#![no_main]
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use hal::clocks::Clock;
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use hal::multicore::{Multicore, Stack};
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use hal::sio::Sio;
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// Ensure we halt the program on panic (if we don't mention this crate it won't
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// be linked)
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use panic_halt as _;
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// Alias for our HAL crate
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use rp2040_hal as hal;
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// A shorter alias for the Peripheral Access Crate, which provides low-level
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// register access
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use hal::pac;
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// Some traits we need
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use embedded_hal::digital::v2::ToggleableOutputPin;
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/// The linker will place this boot block at the start of our program image. We
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2021-12-27 06:29:14 +11:00
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/// need this to help the ROM bootloader get our code up and running.
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2022-09-02 15:38:58 +10:00
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/// Note: This boot block is not necessary when using a rp-hal based BSP
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/// as the BSPs already perform this step.
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2021-12-08 19:34:39 +11:00
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#[link_section = ".boot2"]
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#[used]
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2022-08-11 21:56:36 +10:00
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pub static BOOT2: [u8; 256] = rp2040_boot2::BOOT_LOADER_GENERIC_03H;
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2021-12-08 19:34:39 +11:00
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/// External high-speed crystal on the Raspberry Pi Pico board is 12 MHz. Adjust
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/// if your board has a different frequency
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const XTAL_FREQ_HZ: u32 = 12_000_000u32;
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/// Value to indicate that Core 1 has completed its task
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const CORE1_TASK_COMPLETE: u32 = 0xEE;
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/// Stack for core 1
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///
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/// Core 0 gets its stack via the normal route - any memory not used by static values is
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/// reserved for stack and initialised by cortex-m-rt.
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/// To get the same for Core 1, we would need to compile everything seperately and
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/// modify the linker file for both programs, and that's quite annoying.
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/// So instead, core1.spawn takes a [usize] which gets used for the stack.
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/// NOTE: We use the `Stack` struct here to ensure that it has 32-byte alignment, which allows
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/// the stack guard to take up the least amount of usable RAM.
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static mut CORE1_STACK: Stack<4096> = Stack::new();
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2022-03-05 14:55:32 +11:00
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fn core1_task(sys_freq: u32) -> ! {
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2021-12-08 19:34:39 +11:00
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let mut pac = unsafe { pac::Peripherals::steal() };
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let core = unsafe { pac::CorePeripherals::steal() };
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let mut sio = Sio::new(pac.SIO);
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let pins = hal::gpio::Pins::new(
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pac.IO_BANK0,
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pac.PADS_BANK0,
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sio.gpio_bank0,
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&mut pac.RESETS,
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);
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let mut led_pin = pins.gpio25.into_push_pull_output();
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let mut delay = cortex_m::delay::Delay::new(core.SYST, sys_freq);
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loop {
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let input = sio.fifo.read();
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if let Some(word) = input {
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delay.delay_ms(word);
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led_pin.toggle().unwrap();
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sio.fifo.write_blocking(CORE1_TASK_COMPLETE);
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};
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}
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}
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/// Entry point to our bare-metal application.
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///
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2022-08-22 04:01:45 +10:00
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/// The `#[rp2040_hal::entry]` macro ensures the Cortex-M start-up code calls this function
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/// as soon as all global variables and the spinlock are initialised.
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2021-12-08 19:34:39 +11:00
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///
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/// The function configures the RP2040 peripherals, then toggles a GPIO pin in
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/// an infinite loop. If there is an LED connected to that pin, it will blink.
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2022-08-22 04:01:45 +10:00
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#[rp2040_hal::entry]
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2021-12-08 19:34:39 +11:00
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fn main() -> ! {
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// Grab our singleton objects
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let mut pac = pac::Peripherals::take().unwrap();
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let _core = pac::CorePeripherals::take().unwrap();
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// Set up the watchdog driver - needed by the clock setup code
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let mut watchdog = hal::watchdog::Watchdog::new(pac.WATCHDOG);
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// Configure the clocks
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let clocks = hal::clocks::init_clocks_and_plls(
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XTAL_FREQ_HZ,
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pac.XOSC,
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pac.CLOCKS,
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pac.PLL_SYS,
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pac.PLL_USB,
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&mut pac.RESETS,
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&mut watchdog,
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)
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.ok()
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.unwrap();
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2022-08-19 05:14:51 +10:00
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let sys_freq = clocks.system_clock.freq().to_Hz();
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2022-03-05 14:55:32 +11:00
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2021-12-08 19:34:39 +11:00
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// The single-cycle I/O block controls our GPIO pins
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let mut sio = hal::sio::Sio::new(pac.SIO);
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2022-05-08 18:24:49 +10:00
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let mut mc = Multicore::new(&mut pac.PSM, &mut pac.PPB, &mut sio.fifo);
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2021-12-08 19:34:39 +11:00
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let cores = mc.cores();
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let core1 = &mut cores[1];
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2022-05-08 18:24:49 +10:00
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let _test = core1.spawn(unsafe { &mut CORE1_STACK.mem }, move || {
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core1_task(sys_freq)
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2022-03-05 18:53:11 +11:00
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});
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2021-12-08 19:34:39 +11:00
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/// How much we adjust the LED period every cycle
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const LED_PERIOD_INCREMENT: i32 = 2;
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/// The minimum LED toggle interval we allow for.
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const LED_PERIOD_MIN: i32 = 0;
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/// The maximum LED toggle interval period we allow for. Keep it reasonably short so it's easy to see.
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const LED_PERIOD_MAX: i32 = 100;
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// Our current LED period. It starts at the shortest period, which is the highest blink frequency
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let mut led_period: i32 = LED_PERIOD_MIN;
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// The direction we're incrementing our LED period.
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// Since we start at the minimum value, start by counting up
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let mut count_up = true;
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loop {
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if count_up {
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// Increment our period
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led_period += LED_PERIOD_INCREMENT;
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// Change direction of increment if we hit the limit
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if led_period > LED_PERIOD_MAX {
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led_period = LED_PERIOD_MAX;
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count_up = false;
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}
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} else {
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// Decrement our period
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led_period -= LED_PERIOD_INCREMENT;
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// Change direction of increment if we hit the limit
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if led_period < LED_PERIOD_MIN {
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led_period = LED_PERIOD_MIN;
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count_up = true;
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}
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}
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// It should not be possible for led_period to go negative, but let's ensure that.
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if led_period < 0 {
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led_period = 0;
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}
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// Send the new delay time to Core 1. We convert it
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sio.fifo.write(led_period as u32);
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// Sleep until Core 1 sends a message to tell us it is done
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let ack = sio.fifo.read_blocking();
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if ack != CORE1_TASK_COMPLETE {
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// In a real application you might want to handle the case
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// where the CPU sent the wrong message - we're going to
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// ignore it here.
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}
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}
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}
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// End of file
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