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Fix PWM set/clr_inverted (#122)

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Henrik Lievonen 2021-09-20 05:20:42 +03:00 committed by GitHub
parent ac7a17f6e1
commit 25e477b73e
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1 changed files with 24 additions and 12 deletions
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36
rp2040-hal/src/pwm/mod.rs
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@ -520,18 +520,6 @@ impl<S: SliceId, M: SliceMode, C: ChannelId> Channel<S, M, C> {
duty_cycle,
}
}
/// Invert channel output
#[inline]
pub fn set_inverted(&mut self) {
self.regs.write_inv_b(true)
}
/// Invert channel output or not
#[inline]
pub fn clr_inverted(&mut self) {
self.regs.write_inv_b(false)
}
}
impl<S: SliceId, M: SliceMode, C: ChannelId> Sealed for Channel<S, M, C> {}
@ -603,6 +591,18 @@ impl<S: SliceId, M: SliceMode + ValidSliceMode<S>> Channel<S, M, A> {
pin: pin.into_mode(),
}
}
/// Invert channel output
#[inline]
pub fn set_inverted(&mut self) {
self.regs.write_inv_a(true)
}
/// Stop inverting channel output
#[inline]
pub fn clr_inverted(&mut self) {
self.regs.write_inv_a(false)
}
}
impl<S: SliceId, M: SliceMode + ValidSliceMode<S>> Channel<S, M, B> {
@ -618,6 +618,18 @@ impl<S: SliceId, M: SliceMode + ValidSliceMode<S>> Channel<S, M, B> {
pin: pin.into_mode(),
}
}
/// Invert channel output
#[inline]
pub fn set_inverted(&mut self) {
self.regs.write_inv_b(true)
}
/// Stop inverting channel output
#[inline]
pub fn clr_inverted(&mut self) {
self.regs.write_inv_b(false)
}
}
impl<S: SliceId, M: SliceMode + ValidSliceInputMode<S>> Channel<S, M, B> {