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Set hw reset bits for watchdog

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9names 2022-01-20 21:55:16 +11:00
parent 3a0e23c406
commit 57e9943836
1 changed files with 18 additions and 0 deletions
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18
rp2040-hal/src/watchdog.rs
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@ -92,6 +92,21 @@ impl Watchdog {
fn enable(&self, bit: bool) { fn enable(&self, bit: bool) {
self.watchdog.ctrl.write(|w| w.enable().bit(bit)) self.watchdog.ctrl.write(|w| w.enable().bit(bit))
} }
/// Configure which hardware will be reset by the watchdog
/// the default is everything except ROSC, XOSC
///
/// Safety: ensure no other device is writing to psm.wdsel
/// This is easy at the moment, since nothing else uses PSM
unsafe fn configure_wdog_reset_triggers(&self) {
let psm = &*pac::PSM::ptr();
psm.wdsel.write_with_zero(|w| {
w.bits(0x0001ffff);
w.xosc().clear_bit();
w.rosc().clear_bit();
w
});
}
} }
impl watchdog::Watchdog for Watchdog { impl watchdog::Watchdog for Watchdog {
@ -124,6 +139,9 @@ impl watchdog::WatchdogEnable for Watchdog {
} }
self.enable(false); self.enable(false);
unsafe {
self.configure_wdog_reset_triggers();
}
self.load_counter(self.delay_ms); self.load_counter(self.delay_ms);
self.enable(true); self.enable(true);
} }