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Generate sev in sio.fifo.write()
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@ -109,6 +109,9 @@ impl SioFifo {
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pub fn write(&mut self, value: u32) {
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let sio = unsafe { &(*pac::SIO::ptr()) };
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sio.fifo_wr.write(|w| unsafe { w.bits(value) });
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// Fire off an event to the other core.
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// This is required as the other core may be `wfe` (waiting for event)
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cortex_m::asm::sev();
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}
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/// Read from the inter-core FIFO.
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