The ep0-out buffer must not be marked as available unless required.
Otherwise, the controller will acknowledge the data-out packet but
won't reflect that in its status registers.
This patch forces the controller to nack the data-out phase until we have
processed the setup packet.
As per 4.1.2.5.1, the access to the DPSRAM should "be considered asynchronous
and not atomic".
It is recommended to write to buffer control register in two steps.
A first one to configure all bits but Available.
Wait clk_sys/clk_usb (typically 125MHz/48MHz).
Then set the available bit (if required).
The only thing accessed by those methods is `&mut self`, which is
guaranteed to be a unique reference. So an interrupt can not
interfere with the correctness of the operation.
Implementing `impl From<SystemClock> for Hertz` is a footgun, as
SystemClock is not Copy, so the automatic conversion consumes the
owned clock.
This is visible in the example i2c.rs:
```
let mut i2c = hal::I2C::i2c1(
pac.I2C1,
sda_pin,
scl_pin, // Try `not_an_scl_pin` here
400.kHz(),
&mut pac.RESETS,
clocks.peripheral_clock,
);
```
If the user wants to use both `i2c0` and `i2c1` at the same time,
copying from this example won't work:
```
error[E0382]: use of moved value: `clocks.peripheral_clock`
--> rp2040-hal/examples/i2c.rs:106:9
|
97 | clocks.peripheral_clock,
| ----------------------- value moved here
...
106 | clocks.peripheral_clock,
| ^^^^^^^^^^^^^^^^^^^^^^^ value used here after move
|
= note: move occurs because `clocks.peripheral_clock` has type
`PeripheralClock`, which does not implement the `Copy` trait
```
As getting the frequency from a clock doesn't really need ownership,
changing it to `impl From<&SystemClock> for Hertz` is both more
logical and provides better usability.
This is, however, a breaking change: Code relying on this trait
implementation needs to be changed by adding a `&`.
* Improve comments
* Expose pins and all pins naming struct.
This allows users to set the interrupts on the button pins and to skip the PicoExplorer struct but still use proper naming
* Use correct interrupt names in timer::alarms macro in HAL
* Update changelog, readme and version number for HAL 0.5.0 release
* Bump HAL version in BSP deps
* Point ws2812-pio and i2c-pio-rs at hal_0.5.0 branches
* Update changelog with latest commits and release date
* Change pio::Tx::write to write u32 instead of <T>*
* Add replicated u8/u16 writes to pio::Tx::write
* Switching back to generic version of pio::fifo.write()
* Fix links to make cargo doc happy
Co-authored-by: Jan Niehusmann <jan@gondor.com>
Co-authored-by: Jan Niehusmann <jan@gondor.com>
I managed to avoid the multicore trampoline by messing with the signature of the core 1 startup function.
While the first couple arguments to a function with the arm C abi are passed in registers, once they're filled up, the rest of the arguments go on the stack; so, I put some dummy arguments before the real arguments to force them to go onto the stack. That allows it to be used directly, without needing the trampoline to move the arguments from the stack to registers.
I also changed the startup function to be generic over the function type passed, which avoids the mess of dealing with `Core1Main` and fat pointers and all that.
Using the full module structure generated by the intrinsics macro
interacts oddly with inlining on some optimization levels, causing
a duplicate identical function body to be generated. This doesn't
affect performance, but it wastes space, so just declare the alias
directly which seems to cause the symbol to be aliased as it should
be.
* add example of synchronized PIOs
* Synchronize state machines using WAIT IRQ instruction
* Use "irq wait 0" instead of "wait 1 irq 0"
This way, the initial value of the interrupt flag doesn't matter
* Start state machines synchronized without IRQ WAIT instruction
* Improve API
Co-authored-by: Andrew Straw <strawman@astraw.com>
* Add an rp2040 specific #[entry] macro.
This macro extends the one from cortex-m-rt by code to unlock
all spinlocks on boot.
* Idiomatic pointer arithmetic
Apply suggestion by @9names, improving address calculations.
(This doesn't change the generated code at opt levels 2 or "z".)
Co-authored-by: 9names <60134748+9names@users.noreply.github.com>
* Update BSP authors to include 'rp-rs developers'
* Update BSP readme's to reflect current release version
* Update BSP changelogs
* Fix version number in HAL README
