mirror of
https://github.com/italicsjenga/rp-hal-boards.git
synced 2024-12-25 13:31:31 +11:00
930 lines
30 KiB
Rust
930 lines
30 KiB
Rust
//! Programmable IO (PIO)
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/// See [Chapter 3](https://rptl.io/pico-datasheet) for more details.
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use crate::resets::SubsystemReset;
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use pio::{Program, SideSet, Wrap};
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const PIO_INSTRUCTION_COUNT: usize = 32;
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/// PIO Instance
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pub trait Instance:
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core::ops::Deref<Target = rp2040_pac::pio0::RegisterBlock> + SubsystemReset
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{
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}
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impl Instance for rp2040_pac::PIO0 {}
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impl Instance for rp2040_pac::PIO1 {}
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/// Programmable IO Block
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pub struct PIO<P: Instance> {
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used_instruction_space: core::cell::Cell<u32>, // bit for each PIO_INSTRUCTION_COUNT
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pio: P,
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state_machines: [StateMachine<P>; 4],
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interrupts: [Interrupt<P>; 2],
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}
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impl<P: Instance> core::fmt::Debug for PIO<P> {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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f.debug_struct("PIO")
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.field("used_instruction_space", &self.used_instruction_space)
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.field("pio", &"PIO { .. }")
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.finish()
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}
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}
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// Safety: `PIO` provides exclusive access to PIO registers.
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unsafe impl<P: Instance + Send> Send for PIO<P> {}
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impl<P: Instance> PIO<P> {
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/// Create a new PIO wrapper.
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pub fn new(pio: P, resets: &mut pac::RESETS) -> Self {
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pio.reset_bring_up(resets);
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PIO {
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used_instruction_space: core::cell::Cell::new(0),
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state_machines: [
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StateMachine {
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id: 0,
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block: pio.deref(),
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_phantom: core::marker::PhantomData,
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},
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StateMachine {
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id: 1,
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block: pio.deref(),
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_phantom: core::marker::PhantomData,
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},
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StateMachine {
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id: 2,
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block: pio.deref(),
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_phantom: core::marker::PhantomData,
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},
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StateMachine {
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id: 3,
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block: pio.deref(),
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_phantom: core::marker::PhantomData,
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},
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],
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interrupts: [
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Interrupt {
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id: 0,
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block: pio.deref(),
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_phantom: core::marker::PhantomData,
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},
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Interrupt {
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id: 1,
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block: pio.deref(),
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_phantom: core::marker::PhantomData,
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},
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],
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pio,
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}
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}
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/// Free this instance.
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pub fn free(self) -> P {
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self.pio
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}
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/// This PIO's state machines.
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pub fn state_machines(&self) -> &[StateMachine<P>; 4] {
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&self.state_machines
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}
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/// This PIO's interrupts.
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pub fn interrupts(&self) -> &[Interrupt<P>; 2] {
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&self.interrupts
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}
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/// Clear PIO's IRQ flags indicated by the bits.
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///
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/// The PIO has 8 IRQ flags, of which 4 are visible to the host processor. Each bit of `flags` corresponds to one of
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/// the IRQ flags.
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pub fn clear_irq(&self, flags: u8) {
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self.pio
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.deref()
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.irq
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.write(|w| unsafe { w.irq().bits(flags) });
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}
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/// Force PIO's IRQ flags indicated by the bits.
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///
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/// The PIO has 8 IRQ flags, of which 4 are visible to the host processor. Each bit of `flags` corresponds to one of
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/// the IRQ flags.
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pub fn force_irq(&self, flags: u8) {
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self.pio
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.deref()
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.irq_force
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.write(|w| unsafe { w.irq_force().bits(flags) });
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}
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fn find_offset_for_instructions(&self, i: &[u16], origin: Option<u8>) -> Option<usize> {
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if i.len() > PIO_INSTRUCTION_COUNT {
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None
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} else {
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let mask = (1 << i.len()) - 1;
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if let Some(origin) = origin {
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if origin as usize > PIO_INSTRUCTION_COUNT - i.len()
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|| self.used_instruction_space.get() & (mask << origin) != 0
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{
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None
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} else {
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Some(origin as usize)
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}
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} else {
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for i in (0..=32 - i.len()).rev() {
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if self.used_instruction_space.get() & (mask << i) == 0 {
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return Some(i);
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}
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}
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None
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}
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}
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}
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fn add_program(
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&self,
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instructions: &[u16],
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origin: Option<u8>,
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side_set: pio::SideSet,
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) -> Option<usize> {
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if let Some(offset) = self.find_offset_for_instructions(instructions, origin) {
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for (i, instr) in instructions
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.iter()
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.map(|instr| {
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let mut instr = pio::Instruction::decode(*instr, side_set).unwrap();
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instr.operands = match instr.operands {
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pio::InstructionOperands::JMP { condition, address } => {
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// JMP instruction. We need to apply offset here
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let address = address + offset as u8;
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assert!(
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address < pio::RP2040_MAX_PROGRAM_SIZE as u8,
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"Invalid JMP out of the program after offset addition"
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);
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pio::InstructionOperands::JMP { condition, address }
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}
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_ => instr.operands,
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};
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instr.encode(side_set)
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})
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.enumerate()
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{
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self.pio.instr_mem[i + offset].write(|w| unsafe { w.bits(instr as u32) })
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}
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self.used_instruction_space
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.set(self.used_instruction_space.get() | ((1 << instructions.len()) - 1));
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Some(offset)
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} else {
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None
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}
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}
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}
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/// PIO State Machine.
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#[derive(Debug)]
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pub struct StateMachine<P: Instance> {
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id: u8,
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block: *const rp2040_pac::pio0::RegisterBlock,
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_phantom: core::marker::PhantomData<P>,
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}
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// `StateMachine` doesn't implement `Send` because it sometimes accesses shared registers, e.g. `sm_enable`.
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// unsafe impl<P: Instance + Send> Send for StateMachine<P> {}
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impl<P: Instance> StateMachine<P> {
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/// Start and stop the state machine.
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pub fn set_enabled(&self, enabled: bool) {
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let mask = 1 << self.id;
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if enabled {
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self.block()
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.ctrl
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.modify(|r, w| unsafe { w.sm_enable().bits(r.sm_enable().bits() | mask) })
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} else {
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self.block()
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.ctrl
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.modify(|r, w| unsafe { w.sm_enable().bits(r.sm_enable().bits() & !mask) })
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}
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}
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fn restart(&self) {
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self.block()
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.ctrl
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.write(|w| unsafe { w.sm_restart().bits(1 << self.id) });
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}
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fn reset_clock(&self) {
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self.block()
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.ctrl
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.write(|w| unsafe { w.clkdiv_restart().bits(1 << self.id) });
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}
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fn set_clock_divisor(&self, divisor: f32) {
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// sm frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
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let int = divisor as u16;
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let frac = ((divisor - int as f32) * 256.0) as u8;
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self.sm().sm_clkdiv.write(|w| {
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unsafe {
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w.int().bits(int);
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w.frac().bits(frac);
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}
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w
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});
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}
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/// The address of the instruction currently being executed.
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pub fn instruction_address(&self) -> u32 {
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self.sm().sm_addr.read().bits()
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}
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/// Set the current instruction.
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pub fn set_instruction(&self, instruction: u16) {
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self.sm()
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.sm_instr
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.write(|w| unsafe { w.sm0_instr().bits(instruction) })
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}
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/// Check if the current instruction is stalled.
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pub fn stalled(&self) -> bool {
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self.sm().sm_execctrl.read().exec_stalled().bits()
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}
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fn block(&self) -> &rp2040_pac::pio0::RegisterBlock {
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unsafe { &*self.block }
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}
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fn sm(&self) -> &rp2040_pac::pio0::SM {
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&self.block().sm[self.id as usize]
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}
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/// Get the next element from RX FIFO.
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///
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/// Returns `None` if the FIFO is empty.
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pub fn read_rx(&self) -> Option<u32> {
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let is_empty = self.block().fstat.read().rxempty().bits() & (1 << self.id) != 0;
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if is_empty {
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return None;
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}
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Some(self.block().rxf[self.id as usize].read().bits())
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}
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/// Write an element to TX FIFO.
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///
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/// Returns `true` if the value was written to FIFO, `false` otherwise.
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pub fn write_tx(&self, value: u32) -> bool {
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let is_full = self.block().fstat.read().txfull().bits() & (1 << self.id) != 0;
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if is_full {
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return false;
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}
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self.block().txf[self.id as usize].write(|w| unsafe { w.bits(value) });
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true
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}
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}
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/// PIO Interrupt controller.
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#[derive(Debug)]
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pub struct Interrupt<P: Instance> {
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id: u8,
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block: *const rp2040_pac::pio0::RegisterBlock,
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_phantom: core::marker::PhantomData<P>,
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}
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// Safety: `Interrupt` provides exclusive access to interrupt registers.
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unsafe impl<P: Instance + Send> Send for Interrupt<P> {}
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impl<P: Instance> Interrupt<P> {
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/// Enable interrupts raised by state machines.
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///
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/// The PIO peripheral has 4 outside visible interrupts that can be raised by the state machines. Note that this
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/// don't correspond with the state machine index; any state machine can raise any one of the four interrupts.
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pub fn enable_sm_interrupt(&self, id: u8) {
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match id {
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0 => self.irq().irq_inte.modify(|_, w| w.sm0().set_bit()),
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1 => self.irq().irq_inte.modify(|_, w| w.sm1().set_bit()),
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2 => self.irq().irq_inte.modify(|_, w| w.sm2().set_bit()),
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3 => self.irq().irq_inte.modify(|_, w| w.sm3().set_bit()),
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_ => panic!("invalid state machine interrupt number"),
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}
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}
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/// Disable interrupts raised by state machines.
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///
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/// See [`Self::enable_sm_interrupt`] for info about the index.
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pub fn disable_sm_interrupt(&self, id: u8) {
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match id {
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0 => self.irq().irq_inte.modify(|_, w| w.sm0().clear_bit()),
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1 => self.irq().irq_inte.modify(|_, w| w.sm1().clear_bit()),
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2 => self.irq().irq_inte.modify(|_, w| w.sm2().clear_bit()),
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3 => self.irq().irq_inte.modify(|_, w| w.sm3().clear_bit()),
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_ => panic!("invalid state machine interrupt number"),
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}
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}
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/// Force state machine interrupt.
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///
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/// Note that this doesn't affect the state seen by the state machine. For that, see [`PIO::force_irq`].
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///
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/// See [`Self::enable_sm_interrupt`] for info about the index.
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pub fn force_sm_interrupt(&self, id: u8) {
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match id {
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0 => self.irq().irq_intf.modify(|_, w| w.sm0().set_bit()),
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1 => self.irq().irq_intf.modify(|_, w| w.sm1().set_bit()),
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2 => self.irq().irq_intf.modify(|_, w| w.sm2().set_bit()),
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3 => self.irq().irq_intf.modify(|_, w| w.sm3().set_bit()),
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_ => panic!("invalid state machine interrupt number"),
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}
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}
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/// Enable TX FIFO not full interrupt.
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///
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/// Each of the 4 state machines have their own TX FIFO. This interrupt is raised when the TX FIFO is not full, i.e.
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/// one could push more data to it.
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pub fn enable_tx_not_full_interrupt(&self, id: u8) {
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match id {
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0 => self.irq().irq_inte.modify(|_, w| w.sm0_txnfull().set_bit()),
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1 => self.irq().irq_inte.modify(|_, w| w.sm1_txnfull().set_bit()),
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2 => self.irq().irq_inte.modify(|_, w| w.sm2_txnfull().set_bit()),
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3 => self.irq().irq_inte.modify(|_, w| w.sm3_txnfull().set_bit()),
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_ => panic!("invalid state machine interrupt number"),
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}
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}
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/// Disable TX FIFO not full interrupt.
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///
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/// See [`Self::enable_tx_not_full_interrupt`] for info about the index.
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pub fn disable_tx_not_full_interrupt(&self, id: u8) {
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match id {
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0 => self
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.irq()
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.irq_inte
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.modify(|_, w| w.sm0_txnfull().clear_bit()),
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1 => self
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.irq()
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.irq_inte
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.modify(|_, w| w.sm1_txnfull().clear_bit()),
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2 => self
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.irq()
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.irq_inte
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.modify(|_, w| w.sm2_txnfull().clear_bit()),
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3 => self
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.irq()
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.irq_inte
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.modify(|_, w| w.sm3_txnfull().clear_bit()),
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_ => panic!("invalid state machine interrupt number"),
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}
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}
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/// Force TX FIFO not full interrupt.
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///
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/// See [`Self::enable_tx_not_full_interrupt`] for info about the index.
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pub fn force_tx_not_full_interrupt(&self, id: u8) {
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match id {
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0 => self.irq().irq_intf.modify(|_, w| w.sm0_txnfull().set_bit()),
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1 => self.irq().irq_intf.modify(|_, w| w.sm1_txnfull().set_bit()),
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2 => self.irq().irq_intf.modify(|_, w| w.sm2_txnfull().set_bit()),
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3 => self.irq().irq_intf.modify(|_, w| w.sm3_txnfull().set_bit()),
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_ => panic!("invalid state machine interrupt number"),
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}
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}
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/// Enable RX FIFO not empty interrupt.
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///
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/// Each of the 4 state machines have their own RX FIFO. This interrupt is raised when the RX FIFO is not empty,
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/// i.e. one could read more data from it.
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pub fn enable_rx_not_empty_interrupt(&self, id: u8) {
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match id {
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0 => self
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.irq()
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.irq_inte
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.modify(|_, w| w.sm0_rxnempty().set_bit()),
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1 => self
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.irq()
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.irq_inte
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.modify(|_, w| w.sm1_rxnempty().set_bit()),
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2 => self
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.irq()
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.irq_inte
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.modify(|_, w| w.sm2_rxnempty().set_bit()),
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3 => self
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.irq()
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.irq_inte
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.modify(|_, w| w.sm3_rxnempty().set_bit()),
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_ => panic!("invalid state machine interrupt number"),
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}
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}
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/// Disable RX FIFO not empty interrupt.
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///
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/// See [`Self::enable_rx_not_empty_interrupt`] for info about the index.
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pub fn disable_rx_not_empty_interrupt(&self, id: u8) {
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match id {
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0 => self
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.irq()
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.irq_inte
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.modify(|_, w| w.sm0_rxnempty().clear_bit()),
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1 => self
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.irq()
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.irq_inte
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.modify(|_, w| w.sm1_rxnempty().clear_bit()),
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2 => self
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.irq()
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.irq_inte
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.modify(|_, w| w.sm2_rxnempty().clear_bit()),
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3 => self
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.irq()
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.irq_inte
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.modify(|_, w| w.sm3_rxnempty().clear_bit()),
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_ => panic!("invalid state machine interrupt number"),
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}
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}
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/// Force RX FIFO not empty interrupt.
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///
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/// See [`Self::enable_rx_not_empty_interrupt`] for info about the index.
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pub fn force_rx_not_empty_interrupt(&self, id: u8) {
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match id {
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0 => self
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.irq()
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.irq_intf
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.modify(|_, w| w.sm0_rxnempty().set_bit()),
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1 => self
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.irq()
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.irq_intf
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.modify(|_, w| w.sm1_rxnempty().set_bit()),
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2 => self
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.irq()
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.irq_intf
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.modify(|_, w| w.sm2_rxnempty().set_bit()),
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3 => self
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.irq()
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.irq_intf
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.modify(|_, w| w.sm3_rxnempty().set_bit()),
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_ => panic!("invalid state machine interrupt number"),
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}
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}
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/// Get the raw interrupt state.
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///
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/// This is the state of the interrupts without interrupt masking and forcing.
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pub fn raw(&self) -> InterruptState {
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InterruptState(self.block().intr.read().bits())
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}
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/// Get the interrupt state.
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///
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/// This is the state of the interrupts after interrupt masking and forcing.
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pub fn state(&self) -> InterruptState {
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InterruptState(self.irq().irq_ints.read().bits())
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}
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fn block(&self) -> &rp2040_pac::pio0::RegisterBlock {
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unsafe { &*self.block }
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}
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fn irq(&self) -> &rp2040_pac::pio0::SM_IRQ {
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&self.block().sm_irq[self.id as usize]
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}
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}
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/// Provides easy access for decoding PIO's interrupt state.
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#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)]
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pub struct InterruptState(u32);
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macro_rules! raw_interrupt_accessor {
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($name:ident, $doc:literal, $idx:expr) => {
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#[doc = concat!("Check whether interrupt ", $doc, " has been raised.")]
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pub fn $name(self) -> bool {
|
|
self.0 & (1 << $idx) != 0
|
|
}
|
|
};
|
|
}
|
|
impl InterruptState {
|
|
raw_interrupt_accessor!(sm0_rx_not_empty, "SM0_RXNEMPTY", 0);
|
|
raw_interrupt_accessor!(sm1_rx_not_empty, "SM1_RXNEMPTY", 1);
|
|
raw_interrupt_accessor!(sm2_rx_not_empty, "SM2_RXNEMPTY", 2);
|
|
raw_interrupt_accessor!(sm3_rx_not_empty, "SM3_RXNEMPTY", 3);
|
|
|
|
raw_interrupt_accessor!(sm0_tx_not_full, "SM0_TXNFULL", 4);
|
|
raw_interrupt_accessor!(sm1_tx_not_full, "SM1_TXNFULL", 5);
|
|
raw_interrupt_accessor!(sm2_tx_not_full, "SM2_TXNFULL", 6);
|
|
raw_interrupt_accessor!(sm3_tx_not_full, "SM3_TXNFULL", 7);
|
|
|
|
raw_interrupt_accessor!(sm0, "SM0", 8);
|
|
raw_interrupt_accessor!(sm1, "SM1", 9);
|
|
raw_interrupt_accessor!(sm2, "SM2", 10);
|
|
raw_interrupt_accessor!(sm3, "SM3", 11);
|
|
}
|
|
|
|
/// Comparison used for `mov x, status` instruction.
|
|
#[derive(Debug, Clone, Copy)]
|
|
pub enum MovStatusConfig {
|
|
/// The `mov x, status` instruction returns all ones if TX FIFO level is below the set status, otherwise all zeros.
|
|
Tx(u8),
|
|
/// The `mov x, status` instruction returns all ones if RX FIFO level is below the set status, otherwise all zeros.
|
|
Rx(u8),
|
|
}
|
|
|
|
/// Shift direction for input and output shifting.
|
|
#[derive(Debug, Clone, Copy)]
|
|
pub enum ShiftDirection {
|
|
/// Shift register to left.
|
|
Left,
|
|
/// Shift register to right.
|
|
Right,
|
|
}
|
|
|
|
impl ShiftDirection {
|
|
fn bit(self) -> bool {
|
|
match self {
|
|
Self::Left => false,
|
|
Self::Right => true,
|
|
}
|
|
}
|
|
}
|
|
|
|
/// Builder to deploy a fully configured PIO program on one of the state
|
|
/// machines.
|
|
#[derive(Debug)]
|
|
pub struct PIOBuilder<'a> {
|
|
/// Clock divisor.
|
|
clock_divisor: f32,
|
|
|
|
/// Instructions of the program.
|
|
instructions: &'a [u16],
|
|
/// Origin where this program should be loaded.
|
|
instruction_origin: Option<u8>,
|
|
/// Wrapping behavior.
|
|
wrap: Wrap,
|
|
/// Side-set behavior.
|
|
side_set: SideSet,
|
|
/// GPIO pin used by `jmp pin` instruction.
|
|
jmp_pin: u8,
|
|
|
|
/// Continuously assert the most recent OUT/SET to the pins.
|
|
out_sticky: bool,
|
|
/// Use a bit of OUT data as an auxilary write enable.
|
|
///
|
|
/// When [`out_sticky`](Self::out_sticky) is enabled, setting the bit to 0 deasserts for that instr.
|
|
inline_out: Option<u8>,
|
|
/// Config for `mov x, status` instruction.
|
|
mov_status: MovStatusConfig,
|
|
|
|
/// Config for FIFO joining.
|
|
fifo_join: Buffers,
|
|
|
|
/// Number of bits shifted out of `OSR` before autopull or conditional pull will take place.
|
|
pull_threshold: u8,
|
|
/// Number of bits shifted into `ISR` before autopush or conditional push will take place.
|
|
push_threshold: u8,
|
|
// Shift direction for `OUT` instruction.
|
|
out_shiftdir: ShiftDirection,
|
|
// Shift direction for `IN` instruction.
|
|
in_shiftdir: ShiftDirection,
|
|
// Enable autopull.
|
|
autopull: bool,
|
|
// Enable autopush.
|
|
autopush: bool,
|
|
|
|
/// Number of pins asserted by a `SET`.
|
|
set_count: u8,
|
|
/// Number of pins asserted by an `OUT PINS`, `OUT PINDIRS` or `MOV PINS` instruction.
|
|
out_count: u8,
|
|
/// The first pin that is assigned in state machine's `IN` data bus.
|
|
in_base: u8,
|
|
/// The first pin that is affected by side-set operations.
|
|
side_set_base: u8,
|
|
/// The first pin that is affected by `SET PINS` or `SET PINDIRS` instructions.
|
|
set_base: u8,
|
|
/// The first pin that is affected by `OUT PINS`, `OUT PINDIRS` or `MOV PINS` instructions.
|
|
out_base: u8,
|
|
}
|
|
|
|
impl<'a> Default for PIOBuilder<'a> {
|
|
fn default() -> Self {
|
|
PIOBuilder {
|
|
clock_divisor: 1.0,
|
|
instructions: &[],
|
|
instruction_origin: None,
|
|
wrap: Wrap {
|
|
source: 31,
|
|
target: 0,
|
|
},
|
|
side_set: SideSet::default(),
|
|
jmp_pin: 0,
|
|
out_sticky: false,
|
|
inline_out: None,
|
|
mov_status: MovStatusConfig::Tx(0),
|
|
fifo_join: Buffers::RxTx,
|
|
pull_threshold: 0,
|
|
push_threshold: 0,
|
|
out_shiftdir: ShiftDirection::Left,
|
|
in_shiftdir: ShiftDirection::Left,
|
|
autopull: false,
|
|
autopush: false,
|
|
set_count: 5,
|
|
out_count: 0,
|
|
in_base: 0,
|
|
side_set_base: 0,
|
|
set_base: 0,
|
|
out_base: 0,
|
|
}
|
|
}
|
|
}
|
|
|
|
/// Buffer sharing configuration.
|
|
#[derive(Debug, Clone, Copy)]
|
|
pub enum Buffers {
|
|
/// No sharing.
|
|
RxTx,
|
|
/// The memory of the RX FIFO is given to the TX FIFO to double its depth.
|
|
OnlyTx,
|
|
/// The memory of the TX FIFO is given to the RX FIFO to double its depth.
|
|
OnlyRx,
|
|
}
|
|
|
|
/// Errors that occurred during `PIOBuilder::build`.
|
|
#[derive(Debug)]
|
|
pub enum BuildError {
|
|
/// There was not enough space for the instructions on the selected PIO.
|
|
NoSpace,
|
|
}
|
|
|
|
impl<'a> PIOBuilder<'a> {
|
|
/// Set config settings based on information from the given [`pio::Program`].
|
|
/// Additional configuration may be needed in addition to this.
|
|
pub fn with_program(mut self, p: &'a Program<{ pio::RP2040_MAX_PROGRAM_SIZE }>) -> Self {
|
|
self.instruction_origin = p.origin;
|
|
self.instructions(&p.code).wrap(p.wrap).side_set(p.side_set)
|
|
}
|
|
|
|
/// Set the instructions of the program.
|
|
pub fn instructions(mut self, instructions: &'a [u16]) -> Self {
|
|
self.instructions = instructions;
|
|
self
|
|
}
|
|
|
|
/// Set the wrap source and target.
|
|
///
|
|
/// The program will automatically jump from the wrap bottom to the wrap top in 0 cycles.
|
|
pub fn wrap(mut self, wrap: Wrap) -> Self {
|
|
self.wrap = wrap;
|
|
self
|
|
}
|
|
|
|
/// Set the pins asserted by `SET` instruction.
|
|
///
|
|
/// The least-significant bit of `SET` instruction asserts the state of the pin indicated by `base`, the next bit
|
|
/// asserts the state of the next pin, and so on up to `count` pins. The pin numbers are considered modulo 32.
|
|
pub fn set_pins(mut self, base: u8, count: u8) -> Self {
|
|
assert!(count <= 5);
|
|
self.set_base = base;
|
|
self.set_count = count;
|
|
self
|
|
}
|
|
|
|
/// Set the pins asserted by `OUT` instruction.
|
|
///
|
|
/// The least-significant bit of `OUT` instruction asserts the state of the pin indicated by `base`, the next bit
|
|
/// asserts the state of the next pin, and so on up to `count` pins. The pin numbers are considered modulo 32.
|
|
pub fn out_pins(mut self, base: u8, count: u8) -> Self {
|
|
assert!(count <= 5);
|
|
self.out_base = base;
|
|
self.out_count = count;
|
|
self
|
|
}
|
|
|
|
/// Set the pins used by `IN` instruction.
|
|
///
|
|
/// The `IN` instruction reads the least significant bit from the pin indicated by `base`, the next bit from the
|
|
/// next pin, and so on. The pin numbers are considered modulo 32.
|
|
pub fn in_pin_base(mut self, base: u8) -> Self {
|
|
self.in_base = base;
|
|
self
|
|
}
|
|
|
|
/// Set the pin used by `JMP PIN` instruction.
|
|
///
|
|
/// When the pin set by this function is high, the jump is taken, otherwise not.
|
|
pub fn jmp_pin(mut self, pin: u8) -> Self {
|
|
self.jmp_pin = pin;
|
|
self
|
|
}
|
|
|
|
/// Set the pins used by side-set instructions.
|
|
///
|
|
/// The least-significant side-set bit asserts the state of the pin indicated by `base`, the next bit asserts the
|
|
/// state of the next pin, and so on up to number of bits set using [`Self::side_set`] function.
|
|
pub fn side_set_pin_base(mut self, base: u8) -> Self {
|
|
self.side_set_base = base;
|
|
self
|
|
}
|
|
|
|
/// Set the side-set status.
|
|
pub fn side_set(mut self, side_set: SideSet) -> Self {
|
|
self.side_set = side_set;
|
|
self
|
|
}
|
|
|
|
/// Set buffer sharing.
|
|
///
|
|
/// See [`Buffers`] for more information.
|
|
pub fn buffers(mut self, buffers: Buffers) -> Self {
|
|
self.fifo_join = buffers;
|
|
self
|
|
}
|
|
|
|
/// Set the clock divisor.
|
|
///
|
|
/// The is based on the sys_clk. Set 1 for full speed. A clock divisor of `n` will cause the state machine to run 1
|
|
/// cycle every `n` clock cycles. For small values of `n`, a fractional divisor may introduce unacceptable jitter.
|
|
pub fn clock_divisor(mut self, divisor: f32) -> Self {
|
|
self.clock_divisor = divisor;
|
|
self
|
|
}
|
|
|
|
/// Set the output sticky state.
|
|
///
|
|
/// When the output is set to be sticky, the PIO hardware continuously asserts the most recent `OUT`/`SET` to the
|
|
/// pins.
|
|
pub fn out_sticky(mut self, out_sticky: bool) -> Self {
|
|
self.out_sticky = out_sticky;
|
|
self
|
|
}
|
|
|
|
/// Set the inline `OUT` enable bit.
|
|
///
|
|
/// When set to value, the given bit of `OUT` instruction's data is used as an auxiliary write enable. When used
|
|
/// with [`Self::out_sticky`], writes with enable 0 will deassert the latest pin write.
|
|
pub fn inline_out(mut self, inline_out: Option<u8>) -> Self {
|
|
self.inline_out = inline_out;
|
|
self
|
|
}
|
|
|
|
/// Set the autopush state.
|
|
///
|
|
/// When autopush is enabled, the `IN` instruction automatically pushes the data once the number of bits reaches
|
|
/// threshold set by [`Self::push_threshold`].
|
|
pub fn autopush(mut self, autopush: bool) -> Self {
|
|
self.autopush = autopush;
|
|
self
|
|
}
|
|
|
|
/// Set the number of bits pushed into ISR before autopush or conditional push will take place.
|
|
pub fn push_threshold(mut self, threshold: u8) -> Self {
|
|
self.push_threshold = threshold;
|
|
self
|
|
}
|
|
|
|
/// Set the autopull state.
|
|
///
|
|
/// When autopull is enabled, the `OUT` instruction automatically pulls the data once the number of bits reaches
|
|
/// threshold set by [`Self::pull_threshold`].
|
|
pub fn autopull(mut self, autopull: bool) -> Self {
|
|
self.autopull = autopull;
|
|
self
|
|
}
|
|
|
|
/// Set the number of bits pulled from out of OSR before autopull or conditional pull will take place.
|
|
pub fn pull_threshold(mut self, threshold: u8) -> Self {
|
|
self.pull_threshold = threshold;
|
|
self
|
|
}
|
|
|
|
/// Set the ISR shift direction for `IN` instruction.
|
|
///
|
|
/// For example `ShiftDirection::Right` means that ISR is shifted to right, i.e. data enters from left.
|
|
pub fn in_shift_direction(mut self, direction: ShiftDirection) -> Self {
|
|
self.in_shiftdir = direction;
|
|
self
|
|
}
|
|
|
|
/// Set the OSR shift direction for `OUT` instruction.
|
|
///
|
|
/// For example `ShiftDirection::Right` means that OSR is shifted to right, i.e. data is taken from the right side.
|
|
pub fn out_shift_direction(mut self, direction: ShiftDirection) -> Self {
|
|
self.out_shiftdir = direction;
|
|
self
|
|
}
|
|
|
|
/// Build the config and deploy it to a StateMachine.
|
|
pub fn build<P: Instance>(self, pio: &PIO<P>, sm: &StateMachine<P>) -> Result<(), BuildError> {
|
|
let offset =
|
|
match pio.add_program(self.instructions, self.instruction_origin, self.side_set) {
|
|
Some(o) => o,
|
|
None => return Err(BuildError::NoSpace),
|
|
};
|
|
|
|
// Stop the SM
|
|
// TODO: This should probably do before we write the program source code
|
|
sm.set_enabled(false);
|
|
|
|
// Write all configuration bits
|
|
sm.set_clock_divisor(self.clock_divisor);
|
|
|
|
sm.sm().sm_execctrl.write(|w| {
|
|
w.side_en().bit(self.side_set.optional());
|
|
w.side_pindir().bit(self.side_set.pindirs());
|
|
|
|
unsafe {
|
|
w.jmp_pin().bits(self.jmp_pin);
|
|
}
|
|
|
|
if let Some(inline_out) = self.inline_out {
|
|
w.inline_out_en().bit(true);
|
|
unsafe {
|
|
w.out_en_sel().bits(inline_out);
|
|
}
|
|
} else {
|
|
w.inline_out_en().bit(false);
|
|
}
|
|
|
|
w.out_sticky().bit(self.out_sticky);
|
|
|
|
unsafe {
|
|
w.wrap_top().bits(offset as u8 + self.wrap.source);
|
|
w.wrap_bottom().bits(offset as u8 + self.wrap.target);
|
|
}
|
|
|
|
let n = match self.mov_status {
|
|
MovStatusConfig::Tx(n) => {
|
|
w.status_sel().bit(false);
|
|
n
|
|
}
|
|
MovStatusConfig::Rx(n) => {
|
|
w.status_sel().bit(true);
|
|
n
|
|
}
|
|
};
|
|
unsafe {
|
|
w.status_n().bits(n);
|
|
}
|
|
|
|
w
|
|
});
|
|
|
|
sm.sm().sm_shiftctrl.write(|w| {
|
|
let (fjoin_rx, fjoin_tx) = match self.fifo_join {
|
|
Buffers::RxTx => (false, false),
|
|
Buffers::OnlyTx => (false, true),
|
|
Buffers::OnlyRx => (true, false),
|
|
};
|
|
w.fjoin_rx().bit(fjoin_rx);
|
|
w.fjoin_tx().bit(fjoin_tx);
|
|
|
|
unsafe {
|
|
// TODO: Encode 32 as zero, and error on 0
|
|
w.pull_thresh().bits(self.pull_threshold);
|
|
w.push_thresh().bits(self.push_threshold);
|
|
}
|
|
|
|
w.out_shiftdir().bit(self.out_shiftdir.bit());
|
|
w.in_shiftdir().bit(self.in_shiftdir.bit());
|
|
|
|
w.autopull().bit(self.autopull);
|
|
w.autopush().bit(self.autopush);
|
|
|
|
w
|
|
});
|
|
|
|
sm.sm().sm_pinctrl.write(|w| {
|
|
unsafe {
|
|
w.sideset_count().bits(self.side_set.bits());
|
|
w.set_count().bits(self.set_count);
|
|
w.out_count().bits(self.out_count);
|
|
|
|
w.in_base().bits(self.in_base);
|
|
w.sideset_base().bits(self.side_set_base);
|
|
w.set_base().bits(self.set_base);
|
|
w.out_base().bits(self.out_base);
|
|
}
|
|
|
|
w
|
|
});
|
|
|
|
// Restart SM and its clock
|
|
sm.restart();
|
|
sm.reset_clock();
|
|
|
|
// Set starting location by setting the state machine to execute a jmp
|
|
// to the beginning of the program we loaded in.
|
|
sm.set_instruction(
|
|
pio::InstructionOperands::JMP {
|
|
condition: pio::JmpCondition::Always,
|
|
address: offset as u8,
|
|
}
|
|
.encode(),
|
|
);
|
|
|
|
// Enable SM
|
|
sm.set_enabled(true);
|
|
|
|
Ok(())
|
|
}
|
|
}
|