mirror of
https://github.com/italicsjenga/rp-hal-boards.git
synced 2024-12-25 21:41:31 +11:00
674 lines
20 KiB
Rust
674 lines
20 KiB
Rust
//! Pulse Width Modulation (PWM)
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//!
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//! First you must create a Slices struct which contains all the pwm slices.
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//!
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//! ```no_run
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//! use rp2040_hal::{prelude::*, pwm::{InputHighRunning, Slices}};
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//!
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//!
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//! let mut pac = rp2040_pac::Peripherals::take().unwrap();
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//!
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//! // Init PWMs
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//! let pwm_slices = Slices::new(pac.PWM, &mut pac.RESETS);
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//!
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//! // Configure PWM4
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//! let mut pwm = pwm_slices.pwm4;
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//! pwm.set_ph_correct();
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//! pwm.enable();
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//!
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//! // Set to run when b channel is high
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//! let pwm = pwm.into_mode::<InputHighRunning>();
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//! ```
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//!
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//! Once you have the PWM slice struct, you can add individual pins:
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//!
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//! ```no_run
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//! # use rp2040_hal::{prelude::*, gpio::Pins, sio::Sio, pwm::{InputHighRunning, Slices}};
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//! # let mut pac = rp2040_pac::Peripherals::take().unwrap();
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//! # let pwm_slices = Slices::new(pac.PWM, &mut pac.RESETS);
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//! # let mut pwm = pwm_slices.pwm4.into_mode::<InputHighRunning>();
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//! # let mut pac = rp2040_pac::Peripherals::take().unwrap();
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//! #
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//! # let sio = Sio::new(pac.SIO);
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//! # let pins = Pins::new(
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//! # pac.IO_BANK0,
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//! # pac.PADS_BANK0,
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//! # sio.gpio_bank0,
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//! # &mut pac.RESETS,
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//! # );
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//! #
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//! use embedded_hal::PwmPin;
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//!
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//! // Use B channel (which inputs from GPIO 25)
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//! let mut channel_b = pwm.channel_b;
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//! let channel_pin_b = channel_b.input_from(pins.gpio25);
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//!
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//! // Use A channel (which outputs to GPIO 24)
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//! let mut channel_a = pwm.channel_a;
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//! let channel_pin_a = channel_a.output_to(pins.gpio24);
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//!
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//! // Set duty cycle
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//! channel_a.set_duty(0x00ff);
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//! channel_a.get_duty();
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//! channel_a.set_inverted(); // Invert the output
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//! channel_a.clr_inverted(); // Don't invert the output
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//! ```
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//!
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//! The following configuration options are also available:
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//!
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//! ```no_run
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//! # use rp2040_hal::{prelude::*, pwm::Slices};
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//! # let mut pac = rp2040_pac::Peripherals::take().unwrap();
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//! # let pwm_slices = Slices::new(pac.PWM, &mut pac.RESETS);
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//! # let mut pwm = pwm_slices.pwm4;
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//! pwm.set_ph_correct(); // Run in phase correct mode
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//! pwm.clr_ph_correct(); // Don't run in phase correct mode
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//!
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//! pwm.set_div_int(1u8); // To set integer part of clock divider
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//! pwm.set_div_frac(0u8); // To set fractional part of clock divider
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//!
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//! pwm.get_top(); // To set the TOP register
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//! pwm.set_top(u16::MAX); // To set the TOP register
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//!
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//! ```
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//!
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//! default_config() sets ph_correct to false, the clock divider to 1, does not invert the output, sets top to 65535, and resets the counter.
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//! min_config() leaves those registers in the state they were before it was called (Careful, this can lead to unexpected behavior)
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//! It's recommended to only call min_config() after calling default_config() on a pin that shares a PWM block.
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use core::marker::PhantomData;
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use crate::{
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gpio::{
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bank0::*, FunctionClock, FunctionI2C, FunctionPio0, FunctionPio1, FunctionPwm, FunctionSpi,
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FunctionUart, FunctionUsbAux, FunctionXip, Input, InputConfig, Output, OutputConfig, Pin,
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PinId, PinMode, ValidPinMode,
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},
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resets::SubsystemReset,
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typelevel::Sealed,
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};
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use embedded_hal::PwmPin;
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use pac::PWM;
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pub mod dyn_slice;
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pub use dyn_slice::*;
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mod reg;
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use reg::RegisterInterface;
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/// Used to pin traits to a specific channel (A or B)
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pub trait ChannelId: Sealed {
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/// Corresponding [`DynChannelId`](dyn_slice::DynChannelId)
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const DYN: DynChannelId;
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}
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/// Channel A
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///
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/// These are attached to the even gpio pins and can only do PWM output
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pub enum A {}
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/// Channel B
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///
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/// These are attached to the odd gpio pins and can do PWM output and edge counting for input
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pub enum B {}
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impl ChannelId for A {
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const DYN: DynChannelId = DynChannelId::A;
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}
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impl ChannelId for B {
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const DYN: DynChannelId = DynChannelId::B;
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}
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impl Sealed for A {}
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impl Sealed for B {}
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/// Counter is free-running, and will count continuously whenever the slice is enabled
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pub struct FreeRunning;
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/// Count continuously when a high level is detected on the B pin
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pub struct InputHighRunning;
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/// Count once with each rising edge detected on the B pin
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pub struct CountRisingEdge;
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/// Count once with each falling edge detected on the B pin
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pub struct CountFallingEdge;
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/// Type-level marker for tracking which slice modes are valid for which slices
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pub trait ValidSliceMode<I: SliceId>: Sealed {}
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/// Type-level marker for tracking which slice modes are valid for which slices
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pub trait ValidSliceInputMode<I: SliceId>: Sealed + ValidSliceMode<I> {}
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/// Mode for slice
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pub trait SliceMode: Sealed + Sized {
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/// Corresponding [`DynSliceMode`](dyn_slice::DynSliceMode)
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const DYN: DynSliceMode;
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}
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impl Sealed for FreeRunning {}
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impl SliceMode for FreeRunning {
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const DYN: DynSliceMode = DynSliceMode::FreeRunning;
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}
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impl Sealed for InputHighRunning {}
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impl SliceMode for InputHighRunning {
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const DYN: DynSliceMode = DynSliceMode::InputHighRunning;
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}
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impl Sealed for CountRisingEdge {}
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impl SliceMode for CountRisingEdge {
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const DYN: DynSliceMode = DynSliceMode::CountRisingEdge;
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}
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impl Sealed for CountFallingEdge {}
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impl SliceMode for CountFallingEdge {
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const DYN: DynSliceMode = DynSliceMode::CountFallingEdge;
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}
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impl<I: SliceId> ValidSliceMode<I> for FreeRunning {}
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impl<I: SliceId> ValidSliceMode<I> for InputHighRunning {}
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impl<I: SliceId> ValidSliceMode<I> for CountRisingEdge {}
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impl<I: SliceId> ValidSliceMode<I> for CountFallingEdge {}
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impl<I: SliceId> ValidSliceInputMode<I> for InputHighRunning {}
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impl<I: SliceId> ValidSliceInputMode<I> for CountRisingEdge {}
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impl<I: SliceId> ValidSliceInputMode<I> for CountFallingEdge {}
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//==============================================================================
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// Slice IDs
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//==============================================================================
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/// Type-level `enum` for slice IDs
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pub trait SliceId: Sealed {
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/// Corresponding [`DynSliceId`](dyn_slice::DynSliceId)
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const DYN: DynSliceId;
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/// [`SliceMode`] at reset
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type Reset;
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}
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macro_rules! slice_id {
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($Id:ident, $NUM:literal, $reset : ident) => {
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$crate::paste::paste! {
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#[doc = "Slice ID representing slice " $NUM]
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pub enum $Id {}
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impl Sealed for $Id {}
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impl SliceId for $Id {
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type Reset = $reset;
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const DYN: DynSliceId = DynSliceId { num: $NUM };
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}
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}
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};
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}
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//==============================================================================
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// Registers
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//==============================================================================
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/// Provide a safe register interface for [`Slice`]s
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///
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/// This `struct` takes ownership of a [`SliceId`] and provides an API to
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/// access the corresponding registers.
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struct Registers<I: SliceId> {
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id: PhantomData<I>,
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}
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// [`Registers`] takes ownership of the [`SliceId`], and [`Slice`] guarantees that
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// each slice is a singleton, so this implementation is safe.
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unsafe impl<I: SliceId> RegisterInterface for Registers<I> {
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#[inline]
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fn id(&self) -> DynSliceId {
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I::DYN
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}
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}
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impl<I: SliceId> Registers<I> {
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/// Create a new instance of [`Registers`]
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///
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/// # Safety
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///
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/// Users must never create two simultaneous instances of this `struct` with
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/// the same [`SliceId`]
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#[inline]
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unsafe fn new() -> Self {
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Registers { id: PhantomData }
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}
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/// Provide a type-level equivalent for the
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/// [`RegisterInterface::change_mode`] method.
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#[inline]
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fn change_mode<M: SliceMode + ValidSliceMode<I>>(&mut self) {
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RegisterInterface::do_change_mode(self, M::DYN);
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}
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}
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/// Pwm slice
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pub struct Slice<I, M>
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where
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I: SliceId,
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M: SliceMode + ValidSliceMode<I>,
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{
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regs: Registers<I>,
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mode: PhantomData<M>,
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/// Channel A (always output)
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pub channel_a: Channel<I, M, A>,
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/// Channel B (input or output)
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pub channel_b: Channel<I, M, B>,
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}
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impl<I, M> Slice<I, M>
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where
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I: SliceId,
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M: SliceMode + ValidSliceMode<I>,
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{
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/// Create a new [`Slice`]
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///
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/// # Safety
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///
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/// Each [`Slice`] must be a singleton. For a given [`SliceId`], there must be
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/// at most one corresponding [`Slice`] in existence at any given time.
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/// Violating this requirement is `unsafe`.
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#[inline]
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pub(crate) unsafe fn new() -> Slice<I, M> {
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Slice {
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regs: Registers::new(),
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mode: PhantomData,
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channel_a: Channel::new(0),
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channel_b: Channel::new(0),
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}
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}
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/// Convert the slice to the requested [`SliceMode`]
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#[inline]
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pub fn into_mode<N: SliceMode + ValidSliceMode<I>>(mut self) -> Slice<I, N> {
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if N::DYN != M::DYN {
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self.regs.change_mode::<N>();
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}
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// Safe because we drop the existing slice
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unsafe { Slice::new() }
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}
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/// Set a default config for the slice
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pub fn default_config(&mut self) {
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self.regs.write_ph_correct(false);
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self.regs.write_div_int(1); // No divisor
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self.regs.write_div_frac(0); // No divisor
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self.regs.write_inv_a(false); //Don't invert the channel
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self.regs.write_inv_b(false); //Don't invert the channel
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self.regs.write_top(0xffff); // Wrap at max
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self.regs.write_ctr(0x0000); //Reset the counter
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self.regs.write_cc_a(0); //Default duty cycle of 0%
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self.regs.write_cc_b(0); //Default duty cycle of 0%
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}
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/// Advance the phase with one count
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///
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/// Counter must be running at less than full speed (div_int + div_frac / 16 > 1)
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#[inline]
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pub fn advance_phase(&mut self) {
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self.regs.advance_phase()
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}
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/// Retard the phase with one count
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///
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/// Counter must be running at less than full speed (div_int + div_frac / 16 > 1)
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#[inline]
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pub fn retard_phase(&mut self) {
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self.regs.retard_phase()
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}
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/// Enable phase correct mode
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#[inline]
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pub fn set_ph_correct(&mut self) {
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self.regs.write_ph_correct(true)
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}
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/// Disables phase correct mode
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#[inline]
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pub fn clr_ph_correct(&mut self) {
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self.regs.write_ph_correct(false)
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}
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/// Enable slice
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#[inline]
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pub fn enable(&mut self) {
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self.regs.write_enable(true);
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}
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/// Disable slice
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#[inline]
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pub fn disable(&mut self) {
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self.regs.write_enable(false)
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}
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/// Sets the integer part of the clock divider
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#[inline]
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pub fn set_div_int(&mut self, value: u8) {
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self.regs.write_div_int(value)
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}
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/// Sets the fractional part of the clock divider
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#[inline]
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pub fn set_div_frac(&mut self, value: u8) {
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self.regs.write_div_frac(value)
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}
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/// Get the counter register value
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#[inline]
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pub fn get_counter(&self) -> u16 {
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self.regs.read_ctr()
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}
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/// Set the counter register value
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#[inline]
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pub fn set_counter(&mut self, value: u16) {
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self.regs.write_ctr(value)
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}
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/// Get the top register value
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#[inline]
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pub fn get_top(&self) -> u16 {
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self.regs.read_top()
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}
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/// Sets the top register value
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#[inline]
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pub fn set_top(&mut self, value: u16) {
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self.regs.write_top(value)
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}
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}
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macro_rules! pwm {
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($PWMX:ident, [
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$($SXi:ident: ($slice:literal, [$($pin_a:ident, $pin_b:ident),*], $i:expr)),+
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]) => {
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$(
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slice_id!($SXi, $slice, FreeRunning);
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$(
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impl ValidPwmOutputPin<$SXi, A> for $pin_a {}
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impl ValidPwmOutputPin<$SXi, B> for $pin_b {}
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impl ValidPwmInputPin<$SXi> for $pin_b {}
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)*
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)+
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$crate::paste::paste!{
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/// Collection of all the individual [`Slices`]s
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pub struct Slices {
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_pwm: $PWMX,
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$(
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#[doc = "Slice " $SXi]
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pub [<$SXi:lower>] : Slice<$SXi,<$SXi as SliceId>::Reset>,
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)+
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}
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impl Slices {
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/// Take ownership of the PAC peripheral and split it into discrete [`Slice`]s
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pub fn new(pwm: $PWMX, reset : &mut pac::RESETS) -> Self {
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pwm.reset_bring_up(reset);
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unsafe {
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Self {
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_pwm: pwm,
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$(
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[<$SXi:lower>]: Slice::new(),
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)+
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}
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}
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}
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}
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}
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}
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}
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pwm! {
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PWM, [
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Pwm0: (0, [Gpio0, Gpio1, Gpio16, Gpio17], 0),
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Pwm1: (1, [Gpio2, Gpio3, Gpio18, Gpio19], 1),
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Pwm2: (2, [Gpio4, Gpio5, Gpio20, Gpio21], 2),
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Pwm3: (3, [Gpio6, Gpio7, Gpio22, Gpio23], 3),
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Pwm4: (4, [Gpio8, Gpio9, Gpio24, Gpio25], 4),
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Pwm5: (5, [Gpio10, Gpio11, Gpio26, Gpio27], 5),
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Pwm6: (6, [Gpio12, Gpio13, Gpio28, Gpio29], 6),
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Pwm7: (7, [Gpio14, Gpio15], 7)
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]
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}
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/// Marker trait for valid output pins
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pub trait ValidPwmInputPin<S: SliceId>: Sealed {}
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/// Marker trait for valid input pins (Channel B only)
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pub trait ValidPwmOutputPin<S: SliceId, C: ChannelId>: Sealed {}
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/// Make sure we can't free an GPIO pin while still keeping it attached to pwm
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/// TODO: Maybe FunctionPWM should be private?
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pub trait NonPwmPinMode: Sealed {}
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impl NonPwmPinMode for FunctionClock {}
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impl NonPwmPinMode for FunctionI2C {}
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impl NonPwmPinMode for FunctionPio0 {}
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impl NonPwmPinMode for FunctionPio1 {}
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impl NonPwmPinMode for FunctionSpi {}
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impl NonPwmPinMode for FunctionUart {}
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impl NonPwmPinMode for FunctionUsbAux {}
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impl NonPwmPinMode for FunctionXip {}
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impl<C: InputConfig> NonPwmPinMode for Input<C> {}
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impl<C: OutputConfig> NonPwmPinMode for Output<C> {}
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/// Stores the attached gpio pin.
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///
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/// This value can be ignored/dropped or stored to retrieve the original pin struct
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pub struct PwmPinToken<G: PinId + BankPinId> {
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pin: Pin<G, FunctionPwm>,
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}
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impl<G: PinId + BankPinId> PwmPinToken<G> {
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/// Retrieve the original pin while disconnecting it from the pwm
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pub fn into_mode<N: PinMode + ValidPinMode<G> + NonPwmPinMode>(self) -> Pin<G, N> {
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self.pin.into_mode::<N>()
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}
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}
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impl Slices {
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/// Free the pwm registers from the pwm hal struct while consuming it.
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pub fn free(self) -> PWM {
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self._pwm
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}
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// /// Enable multiple slices at the same time to make their counters sync up.
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// ///
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// /// You still need to call `slice` to get an actual slice
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// pub fn enable_simultaneous<S: SliceId>(&mut self, bits: u8) {
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// // Enable all slices at the same time
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// unsafe {
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// &(*pac::PWM::ptr())
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// .en
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// .modify(|r, w| w.bits(((r.bits() as u8) | bits) as u32));
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// }
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// }
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// /// Get pwm slice based on gpio pin
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// pub fn borrow_mut_from_pin<
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// S: SliceId,
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// C: ChannelId,
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// G: PinId + BankPinId + ValidPwmOutputPin<S, C>,
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// PM: PinMode + ValidPinMode<G>,
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// SM: SliceMode + ValidSliceMode<S>,
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// >(&mut self, _: &Pin<G, PM>) -> &mut Slice<S, SM>{
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// match S::DYN {
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// DynSliceId{num} if num == 0 => &mut self.pwm0,
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// DynSliceId{num} if num == 1 => &mut self.pwm1,
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// DynSliceId{num} if num == 2 => &mut self.pwm2,
|
|
// DynSliceId{num} if num == 3 => &mut self.pwm3,
|
|
// DynSliceId{num} if num == 4 => &mut self.pwm4,
|
|
// DynSliceId{num} if num == 5 => &mut self.pwm5,
|
|
// DynSliceId{num} if num == 6 => &mut self.pwm6,
|
|
// DynSliceId{num} if num == 7 => &mut self.pwm7,
|
|
// _ => unreachable!()
|
|
// }
|
|
// }
|
|
}
|
|
|
|
/// A Channel from the Pwm subsystem.
|
|
///
|
|
/// Its attached to one of the eight slices and can be an A or B side channel
|
|
pub struct Channel<S: SliceId, M: SliceMode, C: ChannelId> {
|
|
regs: Registers<S>,
|
|
slice_mode: PhantomData<M>,
|
|
channel_id: PhantomData<C>,
|
|
duty_cycle: u16,
|
|
}
|
|
|
|
impl<S: SliceId, M: SliceMode, C: ChannelId> Channel<S, M, C> {
|
|
pub(super) unsafe fn new(duty_cycle: u16) -> Self {
|
|
Channel {
|
|
regs: Registers::new(),
|
|
slice_mode: PhantomData,
|
|
channel_id: PhantomData,
|
|
duty_cycle,
|
|
}
|
|
}
|
|
}
|
|
|
|
impl<S: SliceId, M: SliceMode, C: ChannelId> Sealed for Channel<S, M, C> {}
|
|
|
|
impl<S: SliceId, M: SliceMode> PwmPin for Channel<S, M, A> {
|
|
type Duty = u16;
|
|
|
|
/// We cant disable the channel without disturbing the other channel.
|
|
/// So this just sets the duty cycle to zero
|
|
fn disable(&mut self) {
|
|
self.duty_cycle = self.regs.read_cc_a();
|
|
self.regs.write_cc_a(0)
|
|
}
|
|
|
|
fn enable(&mut self) {
|
|
self.regs.write_cc_a(self.duty_cycle)
|
|
}
|
|
|
|
fn get_duty(&self) -> Self::Duty {
|
|
self.regs.read_cc_a()
|
|
}
|
|
|
|
fn get_max_duty(&self) -> Self::Duty {
|
|
self.regs.read_top()
|
|
}
|
|
|
|
fn set_duty(&mut self, duty: Self::Duty) {
|
|
self.regs.write_cc_a(duty)
|
|
}
|
|
}
|
|
|
|
impl<S: SliceId, M: SliceMode> PwmPin for Channel<S, M, B> {
|
|
type Duty = u16;
|
|
|
|
/// We cant disable the channel without disturbing the other channel.
|
|
/// So this just sets the duty cycle to zero
|
|
fn disable(&mut self) {
|
|
self.duty_cycle = self.regs.read_cc_b();
|
|
self.regs.write_cc_b(0)
|
|
}
|
|
|
|
fn enable(&mut self) {
|
|
self.regs.write_cc_b(self.duty_cycle)
|
|
}
|
|
|
|
fn get_duty(&self) -> Self::Duty {
|
|
self.regs.read_cc_b()
|
|
}
|
|
|
|
fn get_max_duty(&self) -> Self::Duty {
|
|
self.regs.read_top()
|
|
}
|
|
|
|
fn set_duty(&mut self, duty: Self::Duty) {
|
|
self.regs.write_cc_b(duty)
|
|
}
|
|
}
|
|
|
|
impl<S: SliceId, M: SliceMode + ValidSliceMode<S>> Channel<S, M, A> {
|
|
/// Capture a gpio pin and use it as pwm output for channel A
|
|
pub fn output_to<
|
|
G: PinId + BankPinId + ValidPwmOutputPin<S, A>,
|
|
PM: PinMode + ValidPinMode<G>,
|
|
>(
|
|
&mut self,
|
|
pin: Pin<G, PM>,
|
|
) -> PwmPinToken<G> {
|
|
PwmPinToken {
|
|
pin: pin.into_mode(),
|
|
}
|
|
}
|
|
|
|
/// Invert channel output
|
|
#[inline]
|
|
pub fn set_inverted(&mut self) {
|
|
self.regs.write_inv_a(true)
|
|
}
|
|
|
|
/// Stop inverting channel output
|
|
#[inline]
|
|
pub fn clr_inverted(&mut self) {
|
|
self.regs.write_inv_a(false)
|
|
}
|
|
}
|
|
|
|
impl<S: SliceId, M: SliceMode + ValidSliceMode<S>> Channel<S, M, B> {
|
|
/// Capture a gpio pin and use it as pwm output for channel B
|
|
pub fn output_to<
|
|
G: PinId + BankPinId + ValidPwmOutputPin<S, B>,
|
|
PM: PinMode + ValidPinMode<G>,
|
|
>(
|
|
&mut self,
|
|
pin: Pin<G, PM>,
|
|
) -> PwmPinToken<G> {
|
|
PwmPinToken {
|
|
pin: pin.into_mode(),
|
|
}
|
|
}
|
|
|
|
/// Invert channel output
|
|
#[inline]
|
|
pub fn set_inverted(&mut self) {
|
|
self.regs.write_inv_b(true)
|
|
}
|
|
|
|
/// Stop inverting channel output
|
|
#[inline]
|
|
pub fn clr_inverted(&mut self) {
|
|
self.regs.write_inv_b(false)
|
|
}
|
|
}
|
|
|
|
impl<S: SliceId, M: SliceMode + ValidSliceInputMode<S>> Channel<S, M, B> {
|
|
/// Capture a gpio pin and use it as pwm input for channel B
|
|
pub fn input_from<G: PinId + BankPinId + ValidPwmInputPin<S>, PM: PinMode + ValidPinMode<G>>(
|
|
&mut self,
|
|
pin: Pin<G, PM>,
|
|
) -> PwmPinToken<G> {
|
|
PwmPinToken {
|
|
pin: pin.into_mode(),
|
|
}
|
|
}
|
|
}
|
|
|
|
impl<S: SliceId, M: SliceMode + ValidSliceMode<S>> Slice<S, M> {
|
|
/// Capture a gpio pin and use it as pwm output
|
|
pub fn output_to<
|
|
G: PinId + BankPinId + ValidPwmOutputPin<S, C>,
|
|
PM: PinMode + ValidPinMode<G>,
|
|
C: ChannelId,
|
|
>(
|
|
&mut self,
|
|
pin: Pin<G, PM>,
|
|
) -> PwmPinToken<G> {
|
|
PwmPinToken {
|
|
pin: pin.into_mode(),
|
|
}
|
|
}
|
|
}
|
|
|
|
impl<S: SliceId, M: SliceMode + ValidSliceInputMode<S>> Slice<S, M> {
|
|
/// Capture a gpio pin and use it as pwm input for channel B
|
|
pub fn input_from<G: PinId + BankPinId + ValidPwmInputPin<S>, PM: PinMode + ValidPinMode<G>>(
|
|
&mut self,
|
|
pin: Pin<G, PM>,
|
|
) -> PwmPinToken<G> {
|
|
PwmPinToken {
|
|
pin: pin.into_mode(),
|
|
}
|
|
}
|
|
}
|