2024-01-11 10:28:01 +11:00
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use std::{
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io::Write,
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sync::{Arc, RwLock},
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time::Duration,
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};
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2024-01-10 15:22:28 +11:00
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use metrics::{describe_gauge, gauge, Gauge};
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2024-01-11 10:28:01 +11:00
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use serde::{Deserialize, Serialize};
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2024-01-10 15:22:28 +11:00
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use serialport::SerialPort;
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2024-01-11 08:57:41 +11:00
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use termcolor::WriteColor;
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2024-01-10 15:22:28 +11:00
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2024-01-12 08:47:21 +11:00
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use crate::errors::PliError;
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2024-01-10 15:22:28 +11:00
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pub struct Pli {
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2024-01-11 10:28:01 +11:00
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pub state: Arc<RwLock<PlState>>,
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port: Box<dyn SerialPort>,
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voltage_gauge: Gauge,
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target_voltage_gauge: Gauge,
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duty_cycle: Gauge,
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internal_charge_current: Gauge,
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internal_load_current: Gauge,
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2024-01-11 10:28:01 +11:00
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regulator_gauges: RegulatorGauges,
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}
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#[derive(Debug, Clone, Copy, Serialize, Deserialize)]
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pub struct PlState {
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pub battery_voltage: f64,
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pub target_voltage: f64,
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pub duty_cycle: f64,
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pub internal_charge_current: f64,
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pub internal_load_current: f64,
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pub regulator_state: RegulatorState,
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}
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impl Default for PlState {
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fn default() -> Self {
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Self {
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battery_voltage: Default::default(),
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target_voltage: Default::default(),
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duty_cycle: Default::default(),
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internal_charge_current: Default::default(),
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internal_load_current: Default::default(),
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regulator_state: RegulatorState::Absorption,
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}
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}
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}
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#[derive(Debug, Clone, Copy, Serialize, Deserialize)]
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pub enum RegulatorState {
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Boost,
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Equalise,
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Absorption,
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Float,
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}
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impl From<u8> for RegulatorState {
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fn from(value: u8) -> Self {
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match value & 0b11 {
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0b00 => Self::Boost,
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0b01 => Self::Equalise,
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0b10 => Self::Absorption,
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0b11 => Self::Float,
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_ => unreachable!(),
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}
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}
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}
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struct RegulatorGauges {
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boost: Gauge,
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equalise: Gauge,
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absorption: Gauge,
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float: Gauge,
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}
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impl RegulatorGauges {
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fn new() -> Self {
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describe_gauge!("pl_regulator", "Regulator state");
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let boost = gauge!("pl_regulator", "state" => "boost");
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let equalise = gauge!("pl_regulator", "state" => "equalise");
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let absorption = gauge!("pl_regulator", "state" => "absorption");
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let float = gauge!("pl_regulator", "state" => "float");
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Self {
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boost,
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equalise,
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absorption,
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float,
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}
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}
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fn set(&mut self, state: &RegulatorState) {
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match state {
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RegulatorState::Boost => {
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self.boost.set(1.);
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self.equalise.set(0.);
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self.absorption.set(0.);
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self.float.set(0.);
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}
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RegulatorState::Equalise => {
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self.boost.set(0.);
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self.equalise.set(1.);
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self.absorption.set(0.);
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self.float.set(0.);
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}
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RegulatorState::Absorption => {
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self.boost.set(0.);
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self.equalise.set(0.);
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self.absorption.set(1.);
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self.float.set(0.);
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}
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RegulatorState::Float => {
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self.boost.set(0.);
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self.equalise.set(0.);
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self.absorption.set(0.);
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self.float.set(1.);
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}
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}
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}
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2024-01-10 15:22:28 +11:00
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}
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2024-01-11 08:57:41 +11:00
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#[derive(Debug, Clone, Copy)]
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pub enum PliRequest {
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ReadRam(u8),
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}
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impl Pli {
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pub fn new(serial_port: String, baud_rate: u32) -> Result<Self, serialport::Error> {
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let port = serialport::new(serial_port, baud_rate)
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.timeout(Duration::from_millis(250))
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.open()?;
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describe_gauge!("pl_battery_voltage", "Battery voltage");
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let voltage_gauge = gauge!("pl_battery_voltage");
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describe_gauge!("pl_target_voltage", "Target voltage");
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let target_voltage_gauge = gauge!("pl_target_voltage");
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describe_gauge!("pl_duty_cycle", "Duty cycle");
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let duty_cycle = gauge!("pl_duty_cycle");
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describe_gauge!("pl_internal_charge_current", "Internal charge current");
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let internal_charge_current = gauge!("pl_internal_charge_current");
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describe_gauge!("pl_internal_load_current", "Internal load current");
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let internal_load_current = gauge!("pl_internal_load_current");
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Ok(Self {
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state: Arc::new(RwLock::new(Default::default())),
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port,
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voltage_gauge,
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target_voltage_gauge,
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duty_cycle,
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internal_charge_current,
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internal_load_current,
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regulator_gauges: RegulatorGauges::new(),
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})
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}
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pub fn refresh(&mut self) {
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match self.read_state() {
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Ok(new_state) => {
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self.voltage_gauge.set(new_state.battery_voltage);
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self.target_voltage_gauge.set(new_state.target_voltage);
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self.duty_cycle.set(new_state.duty_cycle);
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self.internal_charge_current
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.set(new_state.internal_charge_current);
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self.internal_load_current
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.set(new_state.internal_load_current);
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self.regulator_gauges.set(&new_state.regulator_state);
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*self.state.write().expect("PLI state handler panicked!!") = new_state;
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}
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Err(e) => log::error!("State read error: {e:#?}"),
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}
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}
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2024-01-11 08:57:41 +11:00
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pub fn process_request(&mut self, message: PliRequest) {
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match message {
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PliRequest::ReadRam(address) => match self.read_ram(address) {
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Ok(data) => {
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let mut stdout =
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termcolor::StandardStream::stdout(termcolor::ColorChoice::Always);
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let _ = stdout.set_color(
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termcolor::ColorSpec::new().set_fg(Some(termcolor::Color::Green)),
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);
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if writeln!(&mut stdout, "Read RAM at {address}: data {data}").is_err() {
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log::warn!(
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"Failed to set stdout colour\nRead RAM at {address}: data {data}"
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);
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};
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}
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Err(e) => log::error!("RAM read error: {e:?}"),
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},
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}
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}
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2024-01-12 08:47:21 +11:00
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fn read_state(&mut self) -> Result<PlState, PliError> {
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Ok(PlState {
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battery_voltage: (self.read_ram(PlRamAddress::Batv)? as f64) * (4. / 10.),
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target_voltage: (self.read_ram(PlRamAddress::Vreg)? as f64) * (4. / 10.),
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duty_cycle: (self.read_ram(PlRamAddress::Dutycyc)? as f64) / 255.,
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internal_charge_current: (self.read_ram(PlRamAddress::Cint)? as f64) * (4. / 10.),
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internal_load_current: (self.read_ram(PlRamAddress::Lint)? as f64) * (4. / 10.),
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regulator_state: self.read_ram(PlRamAddress::Rstate)?.into(),
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})
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}
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fn send_command(&mut self, req: [u8; 4]) {
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self.port
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.write_all(&req)
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.expect("failed to write to serial port");
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}
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fn receive<const LENGTH: usize>(&mut self) -> [u8; LENGTH] {
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let mut buf = [0; LENGTH];
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match self.port.read_exact(&mut buf) {
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Ok(_) => {}
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Err(e) => log::error!("PLI serial read error: {e:#?}"),
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}
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buf
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}
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2024-01-12 08:47:21 +11:00
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fn read_ram<T>(&mut self, address: T) -> Result<u8, PliError>
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where
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T: Into<u8>,
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{
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self.send_command(command(20, address.into(), 0));
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let buf: [u8; 2] = self.receive();
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if buf[0] == 200 {
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Ok(buf[1])
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} else {
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Err(PliError::ReadError(buf[0]))
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}
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}
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}
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enum PlRamAddress {
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Dutycyc,
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Batv,
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Rstate,
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Vreg,
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Cint,
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Lint,
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}
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impl From<PlRamAddress> for u8 {
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fn from(value: PlRamAddress) -> Self {
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match value {
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PlRamAddress::Dutycyc => 39,
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PlRamAddress::Batv => 50,
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PlRamAddress::Rstate => 101,
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PlRamAddress::Vreg => 105,
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PlRamAddress::Cint => 213,
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PlRamAddress::Lint => 217,
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}
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}
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}
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fn command(operation: u8, address: u8, data: u8) -> [u8; 4] {
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[operation, address, data, !operation]
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}
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