gb-emu/src/processor/memory.rs

291 lines
8.5 KiB
Rust
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use self::rom::ROM;
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use crate::{
processor::{clear_bit, get_bit},
verbose_println,
};
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use minifb::Key;
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use std::io::{stdout, Write};
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use super::SplitRegister;
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pub(crate) mod rom;
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pub(crate) type Address = u16;
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#[derive(Debug, Clone, Copy, PartialEq)]
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enum JoypadBank {
Action,
Direction,
}
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#[derive(Debug, Clone, Copy, PartialEq)]
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struct Joypad {
bank_sel: JoypadBank,
down: bool,
up: bool,
left: bool,
right: bool,
start: bool,
select: bool,
b: bool,
a: bool,
}
impl Joypad {
fn as_register(&self) -> u8 {
let mut reg = 0xFF;
match self.bank_sel {
JoypadBank::Action => {
reg = clear_bit(reg, 5);
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if self.start {
reg = clear_bit(reg, 3);
}
if self.select {
reg = clear_bit(reg, 2);
}
if self.b {
reg = clear_bit(reg, 1);
}
if self.a {
reg = clear_bit(reg, 0);
}
}
JoypadBank::Direction => {
reg = clear_bit(reg, 4);
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if self.down {
reg = clear_bit(reg, 3);
}
if self.up {
reg = clear_bit(reg, 2);
}
if self.left {
reg = clear_bit(reg, 1);
}
if self.right {
reg = clear_bit(reg, 0);
}
}
}
reg
}
}
impl Default for Joypad {
fn default() -> Self {
Self {
bank_sel: JoypadBank::Action,
down: false,
up: false,
left: false,
right: false,
start: false,
select: false,
b: false,
a: false,
}
}
}
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#[allow(dead_code)]
pub struct Memory {
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bootrom: Vec<u8>,
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bootrom_enabled: bool,
rom: ROM,
vram: [u8; 8192],
ram: [u8; 8192],
switchable_ram: [u8; 8192],
cpu_ram: [u8; 128],
oam: [u8; 160],
interrupts: u8,
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pub(super) ime: bool,
pub(super) ime_scheduled: u8,
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io: [u8; 76],
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pub(super) user_mode: bool,
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joypad: Joypad,
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}
impl Memory {
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pub fn init(bootrom: Vec<u8>, bootrom_enabled: bool, rom: ROM) -> Self {
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Self {
bootrom,
bootrom_enabled,
rom,
vram: [0x0; 8192],
ram: [0x0; 8192],
switchable_ram: [0x0; 8192],
cpu_ram: [0x0; 128],
oam: [0x0; 160],
interrupts: 0x0,
ime: false,
ime_scheduled: 0x0,
io: [0xFF; 76],
user_mode: false,
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joypad: Joypad::default(),
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}
}
pub fn get(&self, address: Address) -> u8 {
match address {
0x0..0x8000 => {
// rom access
// todo - switchable rom banks
if self.bootrom_enabled && ((address as usize) < self.bootrom.len()) {
return self.bootrom[address as usize];
} else {
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return self.rom.get(address);
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}
}
0x8000..0xA000 => {
return self.vram[(address - 0x8000) as usize];
}
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0xA000..0xC000 => {
// cart ram
0xFF
}
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0xC000..0xE000 => {
return self.ram[(address - 0xC000) as usize];
}
0xE000..0xFE00 => {
return self.ram[(address - 0xE000) as usize];
}
0xFE00..0xFEA0 => {
return self.oam[(address - 0xFE00) as usize];
}
0xFEA0..0xFF00 => {
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return 0xFF;
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}
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0xFF00..0xFF4C => self.get_io(address),
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0xFF4C..0xFF80 => {
// println!("empty space 2 read");
return 0xFF;
}
0xFF80..0xFFFF => {
return self.cpu_ram[(address - 0xFF80) as usize];
}
0xFFFF => {
return self.interrupts;
}
}
}
pub fn set(&mut self, address: Address, data: u8) {
match address {
0x0..0x8000 => {
// change this with MBC code...
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self.rom.set(address, data);
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}
0x8000..0xA000 => {
self.vram[(address - 0x8000) as usize] = data;
}
0xA000..0xC000 => {
// self.switchable_ram[(address - 0xA000) as usize] = data;
}
0xC000..0xE000 => {
self.ram[(address - 0xC000) as usize] = data;
}
0xE000..0xFE00 => {
self.ram[(address - 0xE000) as usize] = data;
}
0xFE00..0xFEA0 => {
self.oam[(address - 0xFE00) as usize] = data;
}
0xFEA0..0xFF00 => {
// println!("empty space write: {:#X} to addr {:#X}", data, address);
}
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0xFF00..0xFF4C => {
self.set_io(address, data);
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stdout().flush().unwrap();
}
0xFF50 => {
self.bootrom_enabled = false;
}
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0xFF4C..0xFF50 | 0xFF51..0xFF80 => {}
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0xFF80..0xFFFF => {
self.cpu_ram[(address - 0xFF80) as usize] = data;
}
0xFFFF => {
verbose_println!("interrupts set to {:#b}", data);
verbose_println!(" / {:#X}", data);
self.interrupts = data;
}
}
}
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fn get_io(&self, address: Address) -> u8 {
if address == 0xFF00 {
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return self.joypad.as_register();
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}
return self.io[(address - 0xFF00) as usize];
}
fn set_io(&mut self, address: Address, data: u8) {
let addr_l = (address - 0xFF00) as usize;
if !self.user_mode {
self.io[addr_l] = data;
} else {
match address {
0xFF02 => {
if data == 0x81 {
print!("{}", self.get(0xFF01) as char);
stdout().flush().unwrap();
}
}
0xFF04 => self.io[addr_l] = 0,
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0xFF00 => {
// joypad
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if !get_bit(data, 5) {
self.joypad.bank_sel = JoypadBank::Action
}
if !get_bit(data, 4) {
self.joypad.bank_sel = JoypadBank::Direction
}
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}
0xFF11 | 0xFF14 | 0xFF16 | 0xFF19 | 0xFF1E | 0xFF23 | 0xFF26 => {
// sound
self.io[addr_l] = data;
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}
0xFF41 => {
// mixed read/write
self.io[addr_l] = (self.io[addr_l] & 0b00000111) | (data & 0b11111000)
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}
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0xFF4D | 0xFF56 => {
// cgb only
self.io[addr_l] = data;
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}
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0xFF44 | 0xFF76 | 0xFF77 => {
// read-only addresses
println!("BANNED write: {:#X} to {:#X}", data, address);
}
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0xFF46 => {
if data > 0xDF {
panic!("dma transfer out of bounds: {:#X}", data);
}
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self.io[addr_l] = data;
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let mut addr: u16 = 0x0;
addr.set_high(data);
for l in 0x0..0xA0 {
addr.set_low(l);
self.oam[l as usize] = self.get(addr);
}
}
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_ => {
self.io[addr_l] = data;
}
}
}
}
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pub fn update_pressed_keys(&mut self, keys: Vec<Key>) -> bool {
let old = self.joypad.clone();
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self.joypad.down = keys.contains(&Key::Down) || keys.contains(&Key::S);
self.joypad.up = keys.contains(&Key::Up) || keys.contains(&Key::W);
self.joypad.left = keys.contains(&Key::Left) || keys.contains(&Key::A);
self.joypad.right = keys.contains(&Key::Right) || keys.contains(&Key::D);
self.joypad.start = keys.contains(&Key::Equal);
self.joypad.select = keys.contains(&Key::Minus);
self.joypad.a = keys.contains(&Key::Apostrophe);
self.joypad.b = keys.contains(&Key::Semicolon);
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self.joypad != old
}
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}