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90 commits

Author SHA1 Message Date
Andrea Nall 90a6f8414d fix clippy, run fmt 2021-06-27 14:50:06 +10:00
Nic0w 0d19834b2e Change all write to modify 2021-06-27 14:50:06 +10:00
Nic0w 4220b45c24 Cargo fmt 2021-06-27 14:50:06 +10:00
Nic0w ef7f8fe9b7 Initial commit on clocks 2021-06-27 14:50:06 +10:00
jspaulsen c4cd2ffe52 Add documentation to public functions and struct, fix logic issue with max period 2021-06-25 18:18:07 +10:00
jspaulsen c568f0d3df Panic if period exceeds maximum value, fmt 2021-06-25 18:18:07 +10:00
jspaulsen cdd9a553ad Add pause_on_debug, disable watchdog prior to enabling 2021-06-25 18:18:07 +10:00
jspaulsen fe72637972 Fix logic issue with delay_ms 2021-06-25 18:18:07 +10:00
jspaulsen 596bea309b Initial watchdog implementation 2021-06-25 18:18:07 +10:00
Rudo a14cbb5819
Hardware divide/modulo support (#40) 
* Initial SIO div/mod implementation
* Implement signed/unsigned methods for HwDivider
 2021-05-29 22:26:49 +10:00
Andrea Nall 8d0fde20c6 Add SubsystemReset trait to handle subsystem resets 
dd a `SubsystemReset` trait which adds a `reset_bring_up` function to the
relevant PAC types to handle bringing subsystems out of reset.

Also, correct that the PLL and UART modules did not bring the relevant
subsystems out of reset and refactor the GPIO module to use the
SubsystemReset trait.
 2021-05-16 13:12:26 -05:00
Andrea Nall 35464a1c4b typo fix, rustfmt 2021-05-10 08:29:59 -05:00
Andrea Nall 2ef1343c05 add module to manage ownership of parts of SIO 2021-05-09 22:33:36 -05:00
9names 877c967466
Merge pull request #28 from Nic0w/uart 
Working implementation of an UART HAL.
 2021-05-09 18:07:05 +10:00
9names c5da7659c9
Merge pull request #27 from Nic0w/pll 
Working HAL for PLLs
 2021-05-09 17:59:27 +10:00
Nic0w 9b082b012d Clippy, second pass for errors in CI. 2021-05-09 09:53:22 +02:00
Nic0w a663b1f552 Clippy, second pass for errors in CI. 2021-05-09 09:42:31 +02:00
Nic0w e18111d564 Merge branch 'uart' of github.com:Nic0w/rp-hal into uart 2021-05-05 08:10:34 +02:00
Nic0w 020c9d9a3d cargo clippy & fmt 2021-05-05 08:06:47 +02:00
Nic0w c35358f475 Change comment on baudrate calculation 2021-05-05 08:02:53 +02:00
Nic0w 64dee52dd5 Satisfies clippy 2021-05-05 07:55:51 +02:00
9names 72127aa8e7
Remove duplicate entry in Cargo.toml 
Remove accidental duplication of embedded-time dependency introduced when performing merge-conflict resolution
 2021-05-05 12:48:40 +10:00
9names 31b0230da1
Merge branch 'main' into uart 2021-05-05 12:46:06 +10:00
9names d26e13c5ef
Merge branch 'main' into basic-gpio 2021-05-05 08:23:03 +10:00
Nic0w 8586f98c02 Better comments and renamed variable names for more clarity. 2021-05-04 22:16:04 +02:00
Nic0w be78a5c792 Consistency re. clear_bit/set_bit. 2021-05-04 19:56:36 +02:00
Nic0w ac2af7582e Pulling the integer out of the frequency first. 2021-05-04 19:54:15 +02:00
Nic0w d9b1b2b1ec Fix comments on {read,write}_raw() functions 2021-05-04 19:48:40 +02:00
9names 416baf6405 Add #Safety tag to unsafe rationale docstring 2021-05-04 18:08:06 +10:00
9names 7588f76844
Merge branch 'main' into basic-gpio 2021-05-04 16:35:46 +10:00
Nic0w 8d29464ee3 Propagate read errors. 2021-05-02 09:04:05 +02:00
Nic0w 992bcdf47b Cargo fmt 2021-05-02 08:42:51 +02:00
Nic0w abf91a3687 Move serial traits impl. back to uart.rs 2021-05-02 08:41:20 +02:00
Nic0w 835ad7a5c1 Read errors. 2021-05-02 08:27:29 +02:00
Nic0w 5620bdbd07 Move checks in new() so initialize() cannot fail. 2021-04-29 21:06:11 +02:00
Nic0w eb4ebc782a Cargo fmt pass. 2021-04-29 20:35:47 +02:00
Nic0w e91e124484 Merge branch 'pll' of github.com:Nic0w/rp-hal into pll 2021-04-29 20:21:02 +02:00
Nic0w eb376cf47b Using modify() to clear specific bits instead of a blanket 0 on all bits. 2021-04-29 20:16:52 +02:00
Nic0w 5726bef879 Fix typo on post_div check 
Co-authored-by: tdittr <tdittr@users.noreply.github.com>
 2021-04-29 20:16:52 +02:00
Nic0w 20c35d5e14 Fix type conversion issue 2021-04-29 20:16:52 +02:00
Nic0w 649998189f Move PLL parameters into a struct to help testability and reconfiguration of the PLL. 2021-04-29 20:16:52 +02:00
Nic0w 9be7c41400 Working implementation of a PLL HAL. 2021-04-29 20:16:52 +02:00
9names 010a5cabf3 Remove redundant field name 2021-04-29 11:19:47 +10:00
9names f21648de93 Autoformatted using cargo fmt 2021-04-29 11:15:41 +10:00
9names 1b42913077 Remove unneeded unsafe 2021-04-29 11:11:11 +10:00
9names 3bdc338a0d
Merge pull request #29 from tdittr/feature/doc-tests-in-ci 
Add `cargo test` to CI run and fix an error found by it
 2021-04-28 14:02:07 +10:00
9names f728de5efb
Merge pull request #25 from Nic0w/xosc 
Working HAL for the XOSC
 2021-04-28 14:01:10 +10:00
tdittr 39f02c4a44 Add cargo test to CI run and fix an error found by it 
Besides the normal usage of unit-tests this also ensures that
example in doc-comments do at least compile.
 2021-04-27 12:08:47 +02:00
Nic0w f3fba80a71 Implement embedded_hal::serial traits for the UART. 2021-04-26 22:05:37 +02:00
Nic0w 50a428e2ad Error needs to derive Debug if we want to unwrap. 2021-04-26 21:25:52 +02:00