2023-01-15 19:53:15 +11:00
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#![feature(exclusive_range_pattern)]
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2023-01-16 12:13:53 +11:00
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mod processor;
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2023-01-15 19:53:15 +11:00
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use clap::Parser;
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2023-01-16 12:13:53 +11:00
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use processor::CPU;
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2023-01-16 11:35:07 +11:00
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use std::{fs, io};
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2023-01-15 19:53:15 +11:00
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/// Simple program to greet a person
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#[derive(Parser, Debug)]
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#[command(author, version, about, long_about = None)]
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struct Args {
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/// ROM path
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#[arg(short, long)]
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rom: String,
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2023-01-16 11:34:36 +11:00
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/// BootROM path
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#[arg(short, long)]
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bootrom: String,
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2023-01-15 19:53:15 +11:00
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}
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2023-01-15 21:05:28 +11:00
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type Address = u16;
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2023-01-15 19:53:15 +11:00
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type ROM = Vec<u8>;
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2023-01-16 11:34:36 +11:00
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#[derive(Clone, Copy)]
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struct Inner {
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right: u8,
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2023-01-16 12:10:21 +11:00
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left: u8,
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2023-01-16 11:34:36 +11:00
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}
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2023-01-16 14:23:06 +11:00
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#[derive(Clone, Copy)]
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union Register {
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as_u8s: Inner,
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as_u16: u16,
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}
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2023-01-16 12:13:53 +11:00
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pub struct Memory {
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2023-01-15 19:53:15 +11:00
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rom: ROM,
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2023-01-15 20:34:44 +11:00
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vram: [u8; 8192],
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ram: [u8; 8192],
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2023-01-15 19:53:15 +11:00
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}
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impl Memory {
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2023-01-15 20:34:44 +11:00
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fn init(rom: ROM) -> Self {
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Self {
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rom,
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vram: [0x0; 8192],
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ram: [0x0; 8192],
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}
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}
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2023-01-16 12:10:21 +11:00
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2023-01-15 21:05:28 +11:00
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fn get(&self, address: Address) -> u8 {
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2023-01-15 19:53:15 +11:00
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match address {
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0x0..0x8000 => {
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// rom access
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// todo - switchable rom banks
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return self.rom[address as usize];
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}
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0x8000..0xA000 => {
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return self.vram[(address - 0x8000) as usize];
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2023-01-15 19:53:15 +11:00
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}
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0xA000..0xC000 => {
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panic!("switchable ram bank");
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}
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0xC000..0xE000 => {
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return self.ram[(address - 0xC000) as usize];
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2023-01-15 19:53:15 +11:00
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}
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0xE000..0xFE00 => {
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return self.ram[(address - 0xE000) as usize];
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2023-01-15 19:53:15 +11:00
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}
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0xFE00..0xFEA0 => {
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panic!("sprite attrib memory");
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}
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0xFEA0..0xFF00 => {
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panic!("empty")
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}
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0xFF00..0xFF4C => {
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panic!("I/O");
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}
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0xFF4C..0xFF80 => {
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panic!("empty");
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}
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0xFF80..0xFFFF => {
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panic!("internal ram");
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}
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0xFFFF => {
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panic!("interrupt enable register");
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}
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}
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}
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fn set(&mut self, address: Address, data: u8) {
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match address {
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0x0..0x8000 => {
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panic!("tried to write to rom?");
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// self.rom[address as usize] = data;
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}
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0x8000..0xA000 => {
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self.vram[(address - 0x8000) as usize] = data;
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}
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0xA000..0xC000 => {
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panic!("switchable ram bank");
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}
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0xC000..0xE000 => {
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self.ram[(address - 0xC000) as usize] = data;
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}
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0xE000..0xFE00 => {
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self.ram[(address - 0xE000) as usize] = data;
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}
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0xFE00..0xFEA0 => {
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panic!("sprite attrib memory");
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}
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0xFEA0..0xFF00 => {
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panic!("empty")
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}
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0xFF00..0xFF4C => {
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panic!("I/O");
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}
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0xFF4C..0xFF80 => {
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panic!("empty");
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}
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0xFF80..0xFFFF => {
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panic!("internal ram");
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}
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0xFFFF => {
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panic!("interrupt enable register");
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}
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}
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}
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2023-01-15 19:53:15 +11:00
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}
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2023-01-16 12:13:53 +11:00
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pub struct State {
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af: Register,
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bc: Register,
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de: Register,
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hl: Register,
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sp: Register,
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pc: Register,
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}
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impl Default for State {
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fn default() -> Self {
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// default post-bootrom values
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Self {
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af: Register { as_u16: 0x01B0 },
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bc: Register { as_u16: 0x0013 },
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de: Register { as_u16: 0x00D8 },
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hl: Register { as_u16: 0x014D },
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sp: Register { as_u16: 0xFFFE },
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pc: Register { as_u16: 0x0100 },
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}
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}
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}
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fn main() {
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let args = Args::parse();
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let rom: ROM = fs::read(args.rom).expect("Could not load ROM");
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2023-01-16 11:35:07 +11:00
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let _bootrom: ROM = fs::read(args.bootrom).expect("Could not load BootROM");
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2023-01-15 20:34:44 +11:00
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let mut cpu = CPU {
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memory: Memory::init(rom),
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state: State::default(),
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};
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loop {
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cpu.exec_next();
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2023-01-15 19:53:15 +11:00
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}
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}
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2023-01-15 21:05:28 +11:00
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2023-01-16 11:46:00 +11:00
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#[allow(dead_code)]
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2023-01-16 11:34:36 +11:00
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fn pause() {
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io::stdin().read_line(&mut String::new()).unwrap();
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2023-01-15 21:05:28 +11:00
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}
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