Nic0w
ef7f8fe9b7
Initial commit on clocks
2021-06-27 14:50:06 +10:00
jspaulsen
c4cd2ffe52
Add documentation to public functions and struct, fix logic issue with max period
2021-06-25 18:18:07 +10:00
jspaulsen
c568f0d3df
Panic if period exceeds maximum value, fmt
2021-06-25 18:18:07 +10:00
jspaulsen
cdd9a553ad
Add pause_on_debug, disable watchdog prior to enabling
2021-06-25 18:18:07 +10:00
jspaulsen
fe72637972
Fix logic issue with delay_ms
2021-06-25 18:18:07 +10:00
jspaulsen
596bea309b
Initial watchdog implementation
2021-06-25 18:18:07 +10:00
Rudo
a14cbb5819
Hardware divide/modulo support ( #40 )
...
* Initial SIO div/mod implementation
* Implement signed/unsigned methods for HwDivider
2021-05-29 22:26:49 +10:00
9names
9bef0821d9
Merge pull request #38 from anall/bugfix/pll-uart-reset
...
Have the `pll` and `uart` HAL modules bring the hardware out of reset
2021-05-29 20:36:17 +10:00
Andrea Nall
8d0fde20c6
Add SubsystemReset
trait to handle subsystem resets
...
dd a `SubsystemReset` trait which adds a `reset_bring_up` function to the
relevant PAC types to handle bringing subsystems out of reset.
Also, correct that the PLL and UART modules did not bring the relevant
subsystems out of reset and refactor the GPIO module to use the
SubsystemReset trait.
2021-05-16 13:12:26 -05:00
9names
9e7e785e22
Merge pull request #36 from anall/feature/sio
...
add module to manage ownership of parts of SIO
2021-05-12 00:12:45 +10:00
Andrea Nall
35464a1c4b
typo fix, rustfmt
2021-05-10 08:29:59 -05:00
Andrea Nall
2ef1343c05
add module to manage ownership of parts of SIO
2021-05-09 22:33:36 -05:00
9names
877c967466
Merge pull request #28 from Nic0w/uart
...
Working implementation of an UART HAL.
2021-05-09 18:07:05 +10:00
9names
c5da7659c9
Merge pull request #27 from Nic0w/pll
...
Working HAL for PLLs
2021-05-09 17:59:27 +10:00
Nic0w
9b082b012d
Clippy, second pass for errors in CI.
2021-05-09 09:53:22 +02:00
Nic0w
a663b1f552
Clippy, second pass for errors in CI.
2021-05-09 09:42:31 +02:00
Nic0w
e18111d564
Merge branch 'uart' of github.com:Nic0w/rp-hal into uart
2021-05-05 08:10:34 +02:00
Nic0w
020c9d9a3d
cargo clippy & fmt
2021-05-05 08:06:47 +02:00
Nic0w
c35358f475
Change comment on baudrate calculation
2021-05-05 08:02:53 +02:00
Nic0w
64dee52dd5
Satisfies clippy
2021-05-05 07:55:51 +02:00
9names
72127aa8e7
Remove duplicate entry in Cargo.toml
...
Remove accidental duplication of embedded-time dependency introduced when performing merge-conflict resolution
2021-05-05 12:48:40 +10:00
9names
31b0230da1
Merge branch 'main' into uart
2021-05-05 12:46:06 +10:00
9names
19cb392205
Merge pull request #24 from Nitori-/basic-gpio
...
Basic GPIO support
2021-05-05 08:26:21 +10:00
9names
d26e13c5ef
Merge branch 'main' into basic-gpio
2021-05-05 08:23:03 +10:00
9names
e30d4af814
Merge pull request #32 from 9names/ci_improvement
...
CI improvement: separate tasks, disable cargo test, fix clippy warning
2021-05-05 08:22:23 +10:00
Nic0w
8586f98c02
Better comments and renamed variable names for more clarity.
2021-05-04 22:16:04 +02:00
Nic0w
be78a5c792
Consistency re. clear_bit/set_bit.
2021-05-04 19:56:36 +02:00
Nic0w
ac2af7582e
Pulling the integer out of the frequency first.
2021-05-04 19:54:15 +02:00
Nic0w
d9b1b2b1ec
Fix comments on {read,write}_raw() functions
2021-05-04 19:48:40 +02:00
9names
416baf6405
Add #Safety tag to unsafe rationale docstring
2021-05-04 18:08:06 +10:00
9names
691f43c17b
Move tests into seperate workflow
2021-05-04 17:52:48 +10:00
9names
41c6db6811
Move clippy into seperate workflow
2021-05-04 17:41:33 +10:00
9names
95a1080a46
Move rustfmt to seperateworkflow
2021-05-04 17:38:01 +10:00
9names
7588f76844
Merge branch 'main' into basic-gpio
2021-05-04 16:35:46 +10:00
Nic0w
8d29464ee3
Propagate read errors.
2021-05-02 09:04:05 +02:00
Nic0w
992bcdf47b
Cargo fmt
2021-05-02 08:42:51 +02:00
Nic0w
abf91a3687
Move serial traits impl. back to uart.rs
2021-05-02 08:41:20 +02:00
Nic0w
835ad7a5c1
Read errors.
2021-05-02 08:27:29 +02:00
Nic0w
5620bdbd07
Move checks in new() so initialize() cannot fail.
2021-04-29 21:06:11 +02:00
Nic0w
eb4ebc782a
Cargo fmt pass.
2021-04-29 20:35:47 +02:00
Nic0w
e91e124484
Merge branch 'pll' of github.com:Nic0w/rp-hal into pll
2021-04-29 20:21:02 +02:00
Nic0w
eb376cf47b
Using modify() to clear specific bits instead of a blanket 0 on all bits.
2021-04-29 20:16:52 +02:00
Nic0w
5726bef879
Fix typo on post_div check
...
Co-authored-by: tdittr <tdittr@users.noreply.github.com>
2021-04-29 20:16:52 +02:00
Nic0w
20c35d5e14
Fix type conversion issue
2021-04-29 20:16:52 +02:00
Nic0w
649998189f
Move PLL parameters into a struct to help testability and reconfiguration of the PLL.
2021-04-29 20:16:52 +02:00
Nic0w
9be7c41400
Working implementation of a PLL HAL.
2021-04-29 20:16:52 +02:00
9names
48dd8069b8
Merge pull request #30 from 9names/fix_xosc_warning
...
Remove unnecessary unsafe block + cargo fmt XOSC
2021-04-29 17:53:22 +10:00
9names
010a5cabf3
Remove redundant field name
2021-04-29 11:19:47 +10:00
9names
f21648de93
Autoformatted using cargo fmt
2021-04-29 11:15:41 +10:00
9names
1b42913077
Remove unneeded unsafe
2021-04-29 11:11:11 +10:00