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161 commits

Author SHA1 Message Date
Rudo2204 2d1086915c Fix unsigned hardware divide/modulo 2021-07-30 10:50:58 +10:00
Hmvp bcfbd72ed1 Update embedded time 2021-07-27 09:41:03 +10:00
9names 512172179a
Add unsafe blocks around write_with_zero calls (#68) 
The newer version of svd2rust used in the PAC marks write_with_zero calls as unsafe, where the old one did not.
This PR wraps the only 2 calls instances of this in the HAL with unsafe blocks to fix the compile errors.
 2021-07-27 09:31:19 +10:00
Hmvp 4970075974 Also clippy check examples 2021-07-26 20:37:08 +10:00
Hmvp ffa97842e2
Improve clock frequency stuff for uninitialized clocks and add some examples (#64) 
* Improve clock frequency stuff for uninitialized clocks

- Made clocks singletons so the frequency handling actually works as expected
- Added initial frequencies
- Improved the docs
- Added a Clock trait

* Add pico examples.

These have the benefit of knowing which external crystal is attached.
Even though it always should be a 12 MHz crystal.
Thus we can setup the clocks properly

I also changed the rp2040 examples to work out of the box for pico boards since that will probably be used most of the time
 2021-07-26 20:24:58 +10:00
Jonathan Nilsson 148cc2b8ea Warn missing docs, deny in ci 2021-07-25 02:17:43 +10:00
Jonathan Nilsson 1bf47df553 Deny warnings in ci 2021-07-25 02:17:43 +10:00
Jonathan Nilsson 077cba68f5
I2C (#56) 
* I2C implementation based on C SDK

* Basic I2C Example
 2021-07-25 02:16:07 +10:00
Marcuss2 a02c8131ff
Add HD44780 example (#60) 
* Added HD44780 lcd example

* Formatting lcd_display.rs

* Formatting Cargo.toml

* Fixed import formatting issue

* Fixed line with spaces
 2021-07-23 18:37:36 +10:00
Hmvp f310d92b64
Refactor clocks (#54) 
* Remove unneeded lines

* Reduce macro boilerplate

* Refactor clocks
 2021-07-08 20:58:48 +10:00
9names d2aa2b238d Run pwm.rs and pwm_blink.rs through cargo-fmt 2021-07-07 23:55:45 +10:00
Tyler Stowell f87d7ba768
PWM implementation (#44) 
* PWM functionality

* Updated prelude.rs

* Added example, cleaned up the PWM HAL.

* Renamed a file for clarity

* Changes to address C-CTOR recommendations, only 8 PWM channels, restructuring

* Forgot to remove a test function, and added a quick comment.

* Cleaned up code now that PWM channels are clustered in the PAC.
 2021-07-07 23:44:57 +10:00
Hmvp 17e65c4fd5
Initial ADC impl (#52) 
* Initial ADC + temp sensor support
 2021-07-07 23:38:25 +10:00
Andrea Nall 17f8a5ab99
Add 'rt' feature (#53) 
For the HAL, currently just passes the feature to the PAC.

Also pass the 'rt' feature through to the HAL for all the BSP crates.
 2021-07-07 19:33:36 +10:00
Hmvp 614180eda3
Clock init (#49) 
Add preliminary clock init function
 2021-07-07 01:30:44 +10:00
Hmvp 1c6a336104
Spi (#50) 
Add SPI support to the HAL
 2021-07-06 09:42:05 +10:00
Andrea Nall 711c0230b1 fix minor issues 2021-07-03 10:32:43 +10:00
Andrea Nall e3be4f8025 Massive GPIO refactor 
Bring in line with atsamd-hal GPIO v2

Copied as much as possible. Docs lifted mostly as-is.

Also add sample BSP for the Feather RP2040 in boards/feather_rp2040

May include a few random fixes from currently futile attempt to get doctests working.
 2021-07-03 10:32:43 +10:00
Andrea Nall 71a7057b76 split rom_data into safe and unsafe functions 2021-06-29 19:36:19 +10:00
Hmvp e7c2ef39c4 Add missing clocks 
Also reorderd the macro invocations to match the datasheet
 2021-06-29 19:35:08 +10:00
Hmvp 6edfc60960 Fix gpio docs 
The sio argument does not work with a bare pac SIO struct
 2021-06-28 23:18:22 +10:00
Andrea Nall 90a6f8414d fix clippy, run fmt 2021-06-27 14:50:06 +10:00
Nic0w 0d19834b2e Change all write to modify 2021-06-27 14:50:06 +10:00
Nic0w 4220b45c24 Cargo fmt 2021-06-27 14:50:06 +10:00
Nic0w ef7f8fe9b7 Initial commit on clocks 2021-06-27 14:50:06 +10:00
jspaulsen c4cd2ffe52 Add documentation to public functions and struct, fix logic issue with max period 2021-06-25 18:18:07 +10:00
jspaulsen c568f0d3df Panic if period exceeds maximum value, fmt 2021-06-25 18:18:07 +10:00
jspaulsen cdd9a553ad Add pause_on_debug, disable watchdog prior to enabling 2021-06-25 18:18:07 +10:00
jspaulsen fe72637972 Fix logic issue with delay_ms 2021-06-25 18:18:07 +10:00
jspaulsen 596bea309b Initial watchdog implementation 2021-06-25 18:18:07 +10:00
Rudo a14cbb5819
Hardware divide/modulo support (#40) 
* Initial SIO div/mod implementation
* Implement signed/unsigned methods for HwDivider
 2021-05-29 22:26:49 +10:00
Andrea Nall 8d0fde20c6 Add SubsystemReset trait to handle subsystem resets 
dd a `SubsystemReset` trait which adds a `reset_bring_up` function to the
relevant PAC types to handle bringing subsystems out of reset.

Also, correct that the PLL and UART modules did not bring the relevant
subsystems out of reset and refactor the GPIO module to use the
SubsystemReset trait.
 2021-05-16 13:12:26 -05:00
Andrea Nall 35464a1c4b typo fix, rustfmt 2021-05-10 08:29:59 -05:00
Andrea Nall 2ef1343c05 add module to manage ownership of parts of SIO 2021-05-09 22:33:36 -05:00
9names 877c967466
Merge pull request #28 from Nic0w/uart 
Working implementation of an UART HAL.
 2021-05-09 18:07:05 +10:00
9names c5da7659c9
Merge pull request #27 from Nic0w/pll 
Working HAL for PLLs
 2021-05-09 17:59:27 +10:00
Nic0w 9b082b012d Clippy, second pass for errors in CI. 2021-05-09 09:53:22 +02:00
Nic0w a663b1f552 Clippy, second pass for errors in CI. 2021-05-09 09:42:31 +02:00
Nic0w e18111d564 Merge branch 'uart' of github.com:Nic0w/rp-hal into uart 2021-05-05 08:10:34 +02:00
Nic0w 020c9d9a3d cargo clippy & fmt 2021-05-05 08:06:47 +02:00
Nic0w c35358f475 Change comment on baudrate calculation 2021-05-05 08:02:53 +02:00
Nic0w 64dee52dd5 Satisfies clippy 2021-05-05 07:55:51 +02:00
9names 72127aa8e7
Remove duplicate entry in Cargo.toml 
Remove accidental duplication of embedded-time dependency introduced when performing merge-conflict resolution
 2021-05-05 12:48:40 +10:00
9names 31b0230da1
Merge branch 'main' into uart 2021-05-05 12:46:06 +10:00
9names d26e13c5ef
Merge branch 'main' into basic-gpio 2021-05-05 08:23:03 +10:00
Nic0w 8586f98c02 Better comments and renamed variable names for more clarity. 2021-05-04 22:16:04 +02:00
Nic0w be78a5c792 Consistency re. clear_bit/set_bit. 2021-05-04 19:56:36 +02:00
Nic0w ac2af7582e Pulling the integer out of the frequency first. 2021-05-04 19:54:15 +02:00
Nic0w d9b1b2b1ec Fix comments on {read,write}_raw() functions 2021-05-04 19:48:40 +02:00
9names 416baf6405 Add #Safety tag to unsafe rationale docstring 2021-05-04 18:08:06 +10:00
9names 7588f76844
Merge branch 'main' into basic-gpio 2021-05-04 16:35:46 +10:00
Nic0w 8d29464ee3 Propagate read errors. 2021-05-02 09:04:05 +02:00
Nic0w 992bcdf47b Cargo fmt 2021-05-02 08:42:51 +02:00
Nic0w abf91a3687 Move serial traits impl. back to uart.rs 2021-05-02 08:41:20 +02:00
Nic0w 835ad7a5c1 Read errors. 2021-05-02 08:27:29 +02:00
Nic0w 5620bdbd07 Move checks in new() so initialize() cannot fail. 2021-04-29 21:06:11 +02:00
Nic0w eb4ebc782a Cargo fmt pass. 2021-04-29 20:35:47 +02:00
Nic0w e91e124484 Merge branch 'pll' of github.com:Nic0w/rp-hal into pll 2021-04-29 20:21:02 +02:00
Nic0w eb376cf47b Using modify() to clear specific bits instead of a blanket 0 on all bits. 2021-04-29 20:16:52 +02:00
Nic0w 5726bef879 Fix typo on post_div check 
Co-authored-by: tdittr <tdittr@users.noreply.github.com>
 2021-04-29 20:16:52 +02:00
Nic0w 20c35d5e14 Fix type conversion issue 2021-04-29 20:16:52 +02:00
Nic0w 649998189f Move PLL parameters into a struct to help testability and reconfiguration of the PLL. 2021-04-29 20:16:52 +02:00
Nic0w 9be7c41400 Working implementation of a PLL HAL. 2021-04-29 20:16:52 +02:00
9names 010a5cabf3 Remove redundant field name 2021-04-29 11:19:47 +10:00
9names f21648de93 Autoformatted using cargo fmt 2021-04-29 11:15:41 +10:00
9names 1b42913077 Remove unneeded unsafe 2021-04-29 11:11:11 +10:00
9names 3bdc338a0d
Merge pull request #29 from tdittr/feature/doc-tests-in-ci 
Add `cargo test` to CI run and fix an error found by it
 2021-04-28 14:02:07 +10:00
9names f728de5efb
Merge pull request #25 from Nic0w/xosc 
Working HAL for the XOSC
 2021-04-28 14:01:10 +10:00
tdittr 39f02c4a44 Add cargo test to CI run and fix an error found by it 
Besides the normal usage of unit-tests this also ensures that
example in doc-comments do at least compile.
 2021-04-27 12:08:47 +02:00
Nic0w f3fba80a71 Implement embedded_hal::serial traits for the UART. 2021-04-26 22:05:37 +02:00
Nic0w 50a428e2ad Error needs to derive Debug if we want to unwrap. 2021-04-26 21:25:52 +02:00
Jennifer Wilcox 0ff51520f5 Merge branch 'main' of github.com:rp-rs/rp-hal into basic-gpio 2021-04-26 11:57:19 -05:00
Nic0w 920d0dc897 Merge branch 'uart' of github.com:Nic0w/rp-hal into uart 2021-04-26 09:20:22 +02:00
Nic0w 4d949f7310 Multiple changes addressing @tdittr 's comments. 2021-04-26 09:14:32 +02:00
Nic0w aa3fe8fd20 Disable the UART for real when disabling UART. 2021-04-25 20:25:29 +02:00
Nic0w c50a5b6001 Cosmetics. 2021-04-25 20:24:56 +02:00
Nic0w f9254fdffa
Increment byte_written after write has happened. 
Co-authored-by: tdittr <tdittr@users.noreply.github.com>
 2021-04-25 20:00:56 +02:00
Nic0w 2462c430b9
Fix typo on post_div check 
Co-authored-by: tdittr <tdittr@users.noreply.github.com>
 2021-04-25 19:48:09 +02:00
Nic0w c3bc1bbaf8 Fix type conversion issue 2021-04-25 19:45:45 +02:00
Jennifer Wilcox c4ae152fda
Update rp2040-hal/src/gpio.rs 
Co-authored-by: tdittr <tdittr@users.noreply.github.com>
 2021-04-25 12:17:05 -05:00
Jennifer Wilcox eaea9ae1ed Concentrate the unsafe register constructs 
This moves almost all of the unsafe stuff together. The last remaining bit is going to need a PAC fix.
 2021-04-25 12:13:44 -05:00
Jennifer Wilcox 8290368c10 Pull pads out of reset and wait 
We're technically supposed to wait for these resets to finish before poking at registers. This seems to fix the instability I was seeing on the input example especially (TBH I have no idea how it ever worked)
 2021-04-25 11:43:44 -05:00
Jennifer Wilcox 7e45c96a65 Do reset in a good way instead of a wacky way 2021-04-25 11:17:33 -05:00
Jennifer Wilcox b3b7677f82 More review comments 2021-04-25 11:13:21 -05:00
Nic0w 6157ce552f Move PLL parameters into a struct to help testability and reconfiguration of the PLL. 2021-04-25 17:51:03 +02:00
Jennifer Wilcox 037fc665b2
Apply suggestions from code review 
Co-authored-by: tdittr <tdittr@users.noreply.github.com>
 2021-04-25 10:15:32 -05:00
Nic0w 2a704a73f0 Adding blocking helper method to setup the XOSC easily. 2021-04-25 16:34:48 +02:00
Nic0w b9080d0a92 Working implementation of an UART HAL. 2021-04-25 10:51:46 +02:00
Nic0w ff418b0453 Working implementation of a PLL HAL. 2021-04-25 10:12:38 +02:00
Nic0w 8f6aea6a31 Fix compilation issues. 2021-04-25 09:03:20 +02:00
Nic0w 72694a07b5 Fix frequency range check. 2021-04-25 08:58:43 +02:00
Jennifer Wilcox 422a45fbc5 Add documentation 2021-04-24 18:41:12 -05:00
Jennifer Wilcox 94f67f7eca Finish configuration options for IOs 2021-04-24 18:03:03 -05:00
Nic0w d5cbd44ade Fixing calculation bug pointed out by @tdittr 2021-04-25 00:36:46 +02:00
Jennifer Wilcox 3536604b9e Block input reads on Unknown state 2021-04-24 17:28:33 -05:00
Nic0w 568cafe2d1 Multiple changes related to @tdittr 's comments 2021-04-24 23:38:49 +02:00
Jennifer Wilcox 2e5c1fc0e3 Cleanup wacky imports in examples 2021-04-24 16:22:27 -05:00
Jennifer Wilcox 2c3a0956fa Add input support, examples, SIO/PADS ownership 
Sorry this is a large commit :(

This adds support for input pins, including pulling them high or low.

It also adds two examples: the start of a classic blinky LED example, and an example for reading input.
 2021-04-24 16:18:57 -05:00
Nic0w ed1e847618 Remove line as it builds fine without it. 2021-04-24 22:26:26 +02:00
Nic0w d0d9291cde Working HAL for the XOSC 2021-04-24 13:38:17 +02:00