We updated the behavior of boot2 so that there is now no default bootloader.
Pico_explorer_showcase was the only BSP still using git:main, pin
it to the last git commit before https://github.com/rp-rs/rp2040-boot2-rs/pull/7
Fix: The divider for watchdog tick generation is now being set to the
source clock frequency in MHz, instead of the clock frequency in Hz.
Watchdog ticks will now be generated at 1 microsecond intervals
as intended.
* Add standalone UART example
* Add UART example to docs in UART module
* Add core::fmt::write_str to UART module to allow easy use of format! macro in user code
The newer version of svd2rust used in the PAC marks write_with_zero calls as unsafe, where the old one did not.
This PR wraps the only 2 calls instances of this in the HAL with unsafe blocks to fix the compile errors.
* Improve clock frequency stuff for uninitialized clocks
- Made clocks singletons so the frequency handling actually works as expected
- Added initial frequencies
- Improved the docs
- Added a Clock trait
* Add pico examples.
These have the benefit of knowing which external crystal is attached.
Even though it always should be a 12 MHz crystal.
Thus we can setup the clocks properly
I also changed the rp2040 examples to work out of the box for pico boards since that will probably be used most of the time
* PWM functionality
* Updated prelude.rs
* Added example, cleaned up the PWM HAL.
* Renamed a file for clarity
* Changes to address C-CTOR recommendations, only 8 PWM channels, restructuring
* Forgot to remove a test function, and added a quick comment.
* Cleaned up code now that PWM channels are clustered in the PAC.
Bring in line with atsamd-hal GPIO v2
Copied as much as possible. Docs lifted mostly as-is.
Also add sample BSP for the Feather RP2040 in boards/feather_rp2040
May include a few random fixes from currently futile attempt to get doctests working.
dd a `SubsystemReset` trait which adds a `reset_bring_up` function to the
relevant PAC types to handle bringing subsystems out of reset.
Also, correct that the PLL and UART modules did not bring the relevant
subsystems out of reset and refactor the GPIO module to use the
SubsystemReset trait.
